SST39SF040-70-4C-NH.pdf

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

SST39SF010A / 020A / 0405.0V 1Mb / 2Mb / 4Mb (x8) MPF memories

Data Sheet

FEATURES:

• Organized as 128K x8 / 256K x8 / 512K x8

• Single 4.5-5.5V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

(typical values at 14 MHz)

– Active Current: 10 mA (typical)

– Standby Current: 30 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 45 ns

– 70 ns

• Latched Address and Data

• Fast Erase and Byte-Program

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

2 seconds (typical) for SST39SF010A

4 seconds (typical) for SST39SF020A

8 seconds (typical) for SST39SF040

• Automatic Write Timing

– Internal V PP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF010A/020A/040 are CMOS Multi-Purpose

Flash (MPF) manufactured with SST’s proprietary, high

performance CMOS SuperFlash technology. The split-gate

cell design and thick oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST39SF010A/020A/040 devices write

(Program or Erase) with a 4.5-5.5V power supply. The

SST39SF010A/020A/040 devices conform to JEDEC stan-

dard pinouts for x8 memories.

function of the applied voltage, current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. These devices also improve flexibility while lowering

the cost for program, data, and configuration storage appli-

cations.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

Featuring high performance Byte-Program, the

SST39SF010A/020A/040 devices provide a maximum

Byte-Program time of 20 µsec. These devices use Toggle

Bit or Data# Polling to indicate the completion of Program

operation. To protect against inadvertent write, they have

on-chip hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum of

applications, these devices are offered with a guaranteed

typical endurance of 10,000 cycles. Data retention is rated

at greater than 100 years.

To meet high density, surface mount requirements, the

SST39SF010A/020A/040 are offered in 32-lead PLCC and

32-lead TSOP packages. A 600 mil, 32-pin PDIP is also

available. See Figures 1, 2, and 3 for pin assignments.

The SST39SF010A/020A/040 devices are suited for appli-

cations that require convenient and economical updating of

program, configuration, or data memory. For all system

applications, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during erase and program than alter-

native flash technologies. The total energy consumed is a

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The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

is latched on the rising edge of the sixth WE# pulse. The

internal Erase operation begins after the sixth WE# pulse.

The End-of-Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 9 for timing

waveforms. Any commands written during the Sector-

Erase operation will be ignored.

Chip-Erase Operation

The SST39SF010A/020A/040 provide Chip-Erase opera-

tion, which allows the user to erase the entire memory

array to the “1s” state. This is useful when the entire device

must be quickly erased.

Read

The Read operation of the SST39SF010A/020A/040 is

controlled by CE# and OE#, both have to be low for the

system to obtain data from the outputs. CE# is used for

device selection. When CE# is high, the chip is dese-

lected and only standby power is consumed. OE# is the

output control and is used to gate data from the output

pins. The data bus is in high impedance state when

either CE# or OE# is high. Refer to the Read cycle timing

diagram (Figure 4) for further details.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE# or CE#, whichever occurs

first. During the internal Erase operation, the only valid read

is Toggle Bit or Data# Polling. See Table 4 for the command

sequence, Figure 10 for timing diagram, and Figure 18 for

the flowchart. Any commands written during the Chip-

Erase operation will be ignored.

Byte-Program Operation

The SST39SF010A/020A/040 are programmed on a byte-

by-byte basis. Before programming, the sector where the

byte exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load byte address and byte data. During the Byte-

Program operation, the addresses are latched on the falling

edge of either CE# or WE#, whichever occurs last. The

data is latched on the rising edge of either CE# or WE#,

whichever occurs first. The third step is the internal Pro-

gram operation which is initiated after the rising edge of the

fourth WE# or CE#, whichever occurs first. The Program

operation, once initiated, will be completed, within 20 µs.

See Figures 5 and 6 for WE# and CE# controlled Program

operation timing diagrams and Figure 15 for flowcharts.

During the Program operation, the only valid reads are

Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any

commands written during the internal Program operation

will be ignored.

Write Operation Status Detection

The SST39SF010A/020A/040 provide two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system Write cycle time. The

software detection includes two status bits: Data# Polling

(DQ 7 ) and Toggle Bit (DQ 6 ). The End-of-Write detection

mode is enabled after the rising edge of WE# which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ 7 or DQ 6 . In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector basis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand load sequence for Software Data Protection with

Sector-Erase command (30H) and sector address (SA) in

the last bus cycle. The sector address is latched on the fall-

ing edge of the sixth WE# pulse, while the command (30H)

S71147-06-000

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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Data# Polling (DQ 7 )

When the SST39SF010A/020A/040 are in the internal Pro-

gram operation, any attempt to read DQ 7 will produce the

complement of the true data. Once the Program operation

is completed, DQ 7 will produce true data. Note that even

though DQ 7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase opera-

tion, any attempt to read DQ 7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ 7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector- or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling

timing diagram and Figure 16 for a flowchart.

Software Data Protection (SDP)

The SST39SF010A/020A/040 provide the JEDEC

approved Software Data Protection scheme for all data

alteration operations, i.e., Program and Erase. Any Pro-

gram operation requires the inclusion of a series of three-

byte sequence. The three-byte load sequence is used to

initiate the Program operation, providing optimal protection

from inadvertent Write operations, e.g., during the system

power-up or power-down. Any Erase operation requires the

inclusion of six-byte load sequence. The SST39SF010A/

020A/040 devices are shipped with the Software Data Pro-

tection permanently enabled. See Table 4 for the specific

software command codes. During SDP command

sequence, invalid commands will abort the device to read

mode, within T RC.

Product Identification

The Product Identification mode identifies the device as the

SST39SF040, SST39SF010A, or SST39SF020A and

manufacturer as SST. This mode may be accessed by soft-

ware operations. Users may wish to use the software Prod-

uct Identification operation to identify the part (i.e., using the

device ID) when using multiple manufacturers in the same

socket. For details, Table 4 for software operation, Figure

11 for the software ID entry and read timing diagram and

Figure 17 for the ID entry command sequence flowchart.

Toggle Bit (DQ 6 )

During the internal Program or Erase operation, any con-

secutive attempts to read DQ 6 will produce alternating 0s

and 1s, i.e., toggling between 0 and 1. When the internal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Sector- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth

WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-

gram and Figure 16 for a flowchart.

TABLE 1: P RODUCT I DENTIFICATION

Address

Data

Data Protection

The SST39SF010A/020A/040 provide both hardware and

software features to protect nonvolatile data from inadvert-

ent writes.

Manufacturer’s ID

0000H

BFH

Device ID

SST39SF010A

0001H

B5H

SST39SF020A

0001H

B6H

SST39SF040

0001H

B7H

T1.2 1147

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Exit ID command sequence, which

returns the device to the Read operation. Please note that

the software reset command is ignored during an internal

Program or Erase operation. See Table 4 for software com-

mand codes, Figure 12 for timing waveform and Figure 17

for a flowchart.

V DD Power Up/Down Detection: The Write operation is

inhibited when V DD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

S71147-06-000

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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

F UNCTIONAL B LOCK D IAGRAM

X-Decoder

SuperFlash

Memory

Memory Address

Address Buffers & Latches

Y-Decoder

CE#

OE#

Control Logic

I/O Buffers and Data Latches

WE#

DQ 7 - DQ 0

1147 B1.2

SST39SF040

SST39SF020A

SST39SF010A

4 3 2 1 32 31 30

SST39SF010A

SST39SF020A SST39SF040

A14

A13

A11

OE#

A10

CE#

DQ7

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

32-lead PLCC

Top View

14 15 16 17 18 19 20

1147 32-plcc P2.4

FIGURE 1: P IN A SSIGNMENTS FOR 32- LEAD PLCC

S71147-06-000

8/04

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

SST39SF040

SST39SF020A

SST39SF010A

SST39SF020A SST39SF040

A11

A13

A14

A17

WE#

V DD

A18

A16

A15

A12

A11

A13

A14

A17

WE#

V DD

A16

A15

A12

A11

A13

A14

WE#

V DD

A16

A15

A12

Standard Pinout

Top View

Die Up

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V SS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V SS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V SS

DQ2

DQ1

DQ0

1147 32-tsop P1.1

FIGURE 2: P IN A SSIGNMENTS FOR 32- LEAD TSOP (8 MM X 14 MM )

SST39SF040

SST39SF020A

SST39SF010A

SST39SF020A

SST39SF040

A18

A16

A15

A12

DQ0

DQ1

DQ2

V SS

A16

A15

A12

DQ0

DQ1

DQ2

V SS

A16

A15

A12

DQ0

DQ1

DQ2

V SS

32-pin

PDIP

Top View

V DD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V DD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

V DD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

1147 32-pdip P3.2

FIGURE 3: P IN A SSIGNMENTS FOR 32- PIN PDIP

S71147-06-000

8/04

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