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8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16 K ROM/OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI & 2 TIMERS - SDIP42, TQFP44
ST72E121
ST72T121
8-BIT MCU WITH 8 TO 16K OTP/EPROM,
384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS
DATASHEET
n
User Program Memory (OTP/EPROM):
8 to 16K bytes
n
Data RAM: 384 to 512 bytes including 256 bytes
of stack
n
Master Reset and Power-On Reset
n
Low Voltage Detector (LVD) Reset option
n
Run and Power Saving modes
n
32 multifunctional bidirectional I/O lines:
– 9 programmable interrupt inputs
– 4 high sink outputs
– 13 alternate functions
– EMI filtering
PSDIP42
n
Software or Hardware Watchdog (WDG)
n
Two 16-bit Timers, each featuring:
– 2 Input Captures and 2 Output Compares 1)
– External Clock input (on Timer A)
– PWM and Pulse Generator modes
CSDIP42W
Synchronous Serial Peripheral Interface (SPI)
n
n
Asynchronous Serial Communications Interface
(SCI)
n
8-bit Data Manipulation
n
63 basic Instructions and 17 main Addressing
Modes
n
8 x 8 Unsigned Multiply Instruction
True Bit Manipulation
n Complete Development Support on DOS/
WINDOWS TM Real-Time Emulator
n Full Software Package on DOS/WINDOWS TM
(C-Compiler, Cross-Assembler, Debugger)
Note: 1. One only of each on Timer A.
TQFP44
(See ordering information at the end of datasheet)
Device Summary
Features
ST72T121J2
ST72T121J4
Program Memory - bytes
8K
16K
RAM (stack) - bytes
384 (256)
512 (256)
Peripherals
Watchdog, Timers, SPI, SCI and optional Low Voltage Detector Reset
Operating Supply
3 to 5.5 V
CPU Frequency
8MHz max (16MHz oscillator) - 4MHz max over 85
°
C
Temperature Range
- 40
°
C to + 125
C
Package
TQFP44 - SDIP42
OTP/EPROM Devices
ST72T121J4/ST72E121J4
Note : ROM versions are supported by the ST72334/124 family. Important product differences must be taken into account.
Refer to the Preamble in the ST72334/124 Datasheet for more information.
Revision 1.9
May 2001
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . ................................................ 4
1.1 INTRODUCTION . . . . . . . . . . . . . ............................................ 4
1.2 PIN DESCRIPTION . . ..................................................... 5
1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 7
1.4 MEMORY MAP . . . . . . . . . . ................................................ 8
1.5 OPTION BYTE . . . . . . . ................................................... 11
2 CENTRAL PROCESSING UNIT . . ............................................... 12
2.1 INTRODUCTION . . . . . . . . . . . . . ........................................... 12
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 12
2.3 CPU REGISTERS . . . .................................................... 12
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . ........... 15
3.1 CLOCK SYSTEM . . . . . . . . . . . . . ........................................... 15
3.1.1 General Description . . . . . . ........................................... 15
3.1.2 External Clock . . . . . . . . . . . . . ........................................ 15
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 16
3.2.1 Introduction . . . .................................................... 16
3.2.2 External Reset . . . . . . ............................................... 16
3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 16
3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 INTERRUPTS . . ............................................................. 18
4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 18
4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . .............................. 18
4.3 PERIPHERAL INTERRUPTS ............................................... 18
4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 21
4.4.1 Introduction . . . .................................................... 21
4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . ................................. 21
4.4.3 Wait Mode . . . . . . . . . . . . . . . . ........................................ 21
4.4.4 Halt Mode . . . . . .................................................... 22
4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . .................................. 23
5 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 24
5.1 I/O PORTS . . . . . . . . . . . . . . . . . . ........................................... 24
5.1.1 Introduction . . . .................................................... 24
5.1.2 Functional Description . . . . ........................................... 24
5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . ........................... 25
5.1.4 Register Description . . . . . . ........................................... 28
5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.1 Introduction . . . .................................................... 30
5.2.2 Main Features . . . . . . ............................................... 30
5.2.3 Functional Description . . . . ........................................... 30
5.2.4 Hardware Watchdog Option . . . . . . . . . . ................................. 31
5.2.5 Low Power Modes . . . ............................................... 31
5.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 31
5.2.7 Register Description . . . . . . ........................................... 31
5.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................ 33
5.3.1 Introduction . . . .................................................... 33
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Table of Contents
5.3.2 Main Features . . . . . . ............................................... 33
5.3.3 Functional Description . . . . ........................................... 33
5.3.4 Low Power Modes . . ............................................... 45
5.3.5 Interrupts . . . . . .................................................... 45
5.3.6 Summary of Timer modes . . . . . . . . . . . . . . .............................. 45
5.3.7 Register Description . . . . . . ........................................... 46
5.4 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4.1 Introduction . . . .................................................... 51
5.4.2 Main Features . . . . . . ............................................... 51
5.4.3 General Description . . . . . . ........................................... 51
5.4.4 Functional Description . . . . ........................................... 53
5.4.5 Low Power Modes . . . ............................................... 58
5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 58
5.4.7 Register Description . . . . . . ........................................... 59
5.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . ........... 63
5.5.1 Introduction . . . .................................................... 63
5.5.2 Main Features . . . . . . ............................................... 63
5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.5.4 Functional Description . . . . ........................................... 65
5.5.5 Low Power Modes . . . ............................................... 72
5.5.6 Interrupts . . . . . .................................................... 72
5.5.7 Register Description . . . . . . ........................................... 73
6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . ........................................ 76
6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.1 Inherent . . . . . . . . . . . ............................................... 77
6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.3 Direct . ........................................................... 77
6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . ........................... 77
6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.6 Indirect Indexed (Short, Long) . ........................................ 78
6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . ................................. 79
7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . .............................. 82
7.1 ABSOLUTE MAXIMUM RATINGS . . . ........................................ 82
7.2 RECOMMENDED OPERATING CONDITIONS . . . .............................. 83
7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... 84
7.4 RESET CHARACTERISTICS . . . . . . . . . . .................................... 85
7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . .............................. 85
7.6 PERIPHERAL CHARACTERISTICS . . . . . . . .................................. 85
8 GENERAL INFORMATION . . . . . . . . . . ........................................... 89
8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . .............................. 89
8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . ........................... 90
8.3 ORDERING INFORMATION . . . . . . . . . . . . . .................................. 92
9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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ST72E121 ST72T121
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72T121 HCMOS Microcontroller Unit
(MCU) is a member of the ST7 family. The device
is based on an industry-standard 8-bit core and
features an enhanced instruction set. The device
is normally operated at a 16 MHz oscillator fre-
quency. Under software control, the ST72T121
may be placed in either Wait, Slow or Halt modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential. In addition to standard
8-bit data management, the ST72T121 features
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes on the whole mem-
ory. The device includes a low consumption and
fast start on-chip oscillator, CPU, program memo-
ry (OTP/EPROM versions), RAM, 32 I/O lines, a
Low Voltage Detector (LVD) and the following on-
chip peripherals: industry standard synchronous
SPI and asynchronous SCI serial interfaces, digit-
al Watchdog, two independent 16-bit Timers, one
featuring an External Clock Input, and both featur-
ing Pulse Generator capabilities, 2 Input Captures
and 2 Output Compares (only 1 Input Capture and
1 Output Compare on Timer A).
Figure 1. ST72T121 Block Diagram
OSCIN
OSCOUT
OSC
Internal
CLOCK
PORT A
PA3 -> PA7
(5 bits)
RESET
CONTROL
AND LVD
PORT B
PB0 -> PB4
(5 bits)
8-BIT CORE
ALU
TIMER B
PORT C
PC0 -> PC7
(8 bits)
PROGRAM
SPI
MEMORY
(8 - 16K Bytes)
PORT D
PD0 -> PD5
RAM
(384 - 512 Bytes)
(6 bits)
PORT E
PF0 -> PF2,4,6,7
PORT F
PE0 -> PE1
(2 bits)
(6 bits)
SCI
TIMER A
V DD
POWER
SUPPLY
WATCH DOG
V SS
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ST72E121 ST72T121
1.2 PIN DESCRIPTION
Figure 2. 44-Pin Thin QFP Package Pinout
PE1/RDI
1
2
3
4
5
6
7
8
9
10
11
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
V SS_1
V DD_1
PA3
PB0
(EI2)
(EI2)
(EI2)
(EI2)
PB1
(EI0)
PB2
PC7/SS
PC6/SCK
PB3
PB4
PD0
(EI3)
PC5/MOSI
PC4/MISO
PD1
PD2
PD3
PD4
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B
12 13 14 15 16 17 18 19
20 21 22
1. V PP on EPR OM/OTP only
Figure 3. 42-Pin Shrink DIP Package Pinout
PB4
PD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(EI3)
(EI2)
42
41
40
39
38
37
36
35
PB3
PB2
PB1
PB0
(EI2)
PD1
PD2
PD3
(EI2)
(EI2)
PE1/RDI
PD4
PE0/TD0
V D D_2
OSCIN
OSCOUT
V SS_2
V DD_3
V SS_3
34
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
(EI1)
(EI1)
(EI1)
33
32
RESET
TEST/V PP 1)
PA7
PA6
PA5
31
30
29
EXTCLK_A/PF7
15
16
17
18
19
20
21
28
27
26
25
24
23
22
PC0/OCMP2_B
PA4
V SS_1
V D D_1
PA3
PC1/OCMP1_B
PC2/ICAP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
(EI0)
PC7/SS
PC6/SCK
1. V PP on EPR OM/OTP only
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