X55020.PDF

Preliminary Information

X55020

Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

FEATURES

DESCRIPTION

fail indicator

• Active high and active low reset outputs

• Selectable watchdog timer

—(0.15s, 0.4s, 0.8s, off)

•Low V

This device combines power-on reset control, battery

switch circuit, watchdog timer, supply voltage supervi-

sion, secondary voltage supervision, and 4Kbit serial

EEPROM in one package. This combination lowers

system cost, reduces board space requirements, and

increases reliability.

(V1MON) and V2MON detection and

reset assertion

—Four standard reset threshold voltages

—Re-program V1

Applying power to the de vice ac tivates the power on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

reset threshold

voltage using special programming sequence

—Reset signal valid to V

TRIP

and V2

TRIP

= 1V

• Long battery life with low power consumption

—<50µA max standby current, watchdog on

—<30µA max standby current, watchdog off

—<1.5mA max active current during read

• 4Kbits of EEPROM

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—In circuit programmable ROM mode

• 10MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

—64-byte page write mode

—Self-timed write cycle

—5ms write cycle time (typical)

• 2.7V to 5.5V power supply operation

• Available packages

—20-lead TSSOP

A system battery switch circuit compares V

whichever is higher. This provides voltage to external

SRAM or other circuits in the event of main power fail-

ure. The X55020 can drive 50mA from V

input and connects V

BATT

OUT

and 250µA

from V

. The device switches to V

when V

BATT

drops below the low V

voltage threshold and V

BATT

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a s electable

time-out interval, the device activates the RESET/

RESET signal. The user selects the interval from three

preset values. Once selected, the interval does not

change, even after cycling the power.

detection circuitry protects the

user’s system from low voltage conditions, resetting the

system when V

(V1MO N) falls below the minimum

trip point (V1

). RESET/RESET is asserted

TRIP

returns to proper operating level and stabi-

lizes. A second voltage monitor circuit tracks the unreg-

ulated supply or monitors a second power supply

voltage to provide a power fail warning. Xicor’s unique

circuits allow the threshold for either voltage monitor to

be reprogrammed to meet special needs or to ﬁne-tune

the threshold for applications requiring higher precision.

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Characteristics subject to change without notice.

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• Dual voltage monitoring

• System battery switch-over circuitry

• Early warning low V

(V1MON) with V

The device’s low V

until V

X55020 – Preliminary Information

BLOCK DIAGRAM

V2MON

V2FAIL

V2 TRIP

V2 Monitor

Logic

Watchdog Transition

Detector

Watchdog

Timer Reset

Protect Logic

Data

RESET

Status

Command

Decode, Test

& Control

Logic

EEPROM Array

Reset &

Watchdog

Timebase

SCK

8 X 512

RESET

BATT-ON

System

Battery

Switch

V BATT

Power On,

Low Voltage

V CC

Reset

V1 TRIP

(V1MON)

V CC Monitor

Generation

Logic

LOWLINE

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Characteristics subject to change without notice.

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V OUT

X55020 – Preliminary Information

PIN CONFIGURATION

20-Pin TSSOP

CS/WDI

V CC (V1MON)

RESET

BATT-ON

LOWLINE

V OUT

V2FAIL

V BATT

SCK

V2MON

V SS

Name

Function

S/WDI

CS HIGH, deselects the device and the SO output pin is at a high impedance

sta te. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.

CS LOW enables the device, placing it in the acti ve p ower mode. Prior to the start of any opera-

tion after power up, a HIGH to LOW transition on CS is required.

A HIGH to LOW transition on the WDI pin restarts the Watch dog time r. The

absence of a HIGH to LOW transition within the watchdog time-out period results in RESET/RESET

going active.

No internal connections

SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

RESET

Reset Output

RESET is an active HIGH, CMOS output which is the inverse of the RESET out-

put.

LOWLINE

Early Low V

Detect

This CMOS output signal goes LOW when V

< V1

TRIP

and returns

HIGH when V

> V1

. This pin goes LOW 250ns before RESET pin.

TRIP

V2FAIL

V2 Voltage Fail Output.

This open drain output goes LOW when V2MON is less than V2

TRIP

. There is no power up reset delay circuitry on this

pin. This circuit works independently from the Low V

TRIP

reset and battery switch circuits.

V2MON

voltage, V2FAIL goes

LOW. This input can monitor an unregulated power supply with an external resistor divider or can

monitor a second power supply with no external components. Connect V2MON to V

When the V2MON input is less than the V2

TRIP

or V

when not used.

The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the Watchdog Timer control and the memory write protect bits. This pin is also used as the test

mode enable pin where the high voltage will be applied. Thus the layout for the input is different

to allow for higher punch thru.

No internal connections

Ground

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Characteristics subject to change without notice.

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Chip Select Input.

Watchdog Input.

Serial Output.

and goes HIGH when V2MON exceeds V2

V2 Voltage Monitor Input.

Write Protect.

X55020 – Preliminary Information

Name

Function

SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on

this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),

addresses and data MSB ﬁrst.

No internal connections

SCK

The Serial Clock controls the serial bus timing for data input and output. The rising

edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of

SCK changes the data output on the SO pin.

BATT

Battery Supply Voltage.

This input provides a backup supply in the event of a failure of the pri-

voltage typically provides the supply voltage necessary to main-

tain the contents of SRAM and also powers the internal logic to “stay awake.”

voltage. The V

BATT

OUT

Output Voltage.

OUT

= V

if V

> V1

TRIP

. IF V

< V1

TRIP

, then V

OUT

= V

if V

+ 0.03, or V

= V

if V

< V

– 0.03.

BATT

OUT

BATT

± 0.03V point to avoid oscillation at or near the switcho-

ver voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.

There is hysteresis around V

BATT

BATT-ON

Battery On.

This CMOS output goes HIGH when the V

OUT

switches to V

BATT

and goes LOW

when V

switches to V

. It is used to drive an external PNP pass transistor when V

= V

OUT

and current requirements are greater than 50mA.

The purpose of this output is to drive an external transistor to get higher operating currents when

the V

supply is fully functional. In the event of a V

failure, the battery voltage is applied to

pin and the external transistor is turned off. In this “backup condition,” the battery only

needs to supply enough voltage and current to keep SRAM devices from losing their data-there

is no communication at this time.

OUT

RESET

RESET Output

This is an active LOW, open drain output which goes active whenever V

falls

below the minimum V

sense level. Then communication to the device is interr upted. It will remain

sense level for 150ms. RESET goes active if the

Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable

Watchdog time-out period. RESET also goes active on power up and remains active for 150ms

after the power supply stabilizes.

rises above the min imum V

No internal connections

Supply Voltage

(V1MON)

V1 Voltage Monitor Input.

When the V1MON input is less than the V1

TRIP

voltage, RESET and

RESET goes ACTIVE.

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Characteristics subject to change without notice.

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Serial Input.

Serial Clock.

mary V

Note:

the V

active until V

X55020 – Preliminary Information

PRINCIPLES OF OPERATION

RESET signal remains active until the voltage drops

below 1V. These also remain active until V CC returns

and exceeds V1 TRIP for 150ms.

Power On Reset

Application of power to the X55020 activates a Power

On Reset Cir cuit. Th is circuit goes active at about 1V

and pulls the RESET/RESET pin active. This signal pre-

vents the system microprocessor from starting to oper-

ate with insufﬁcient voltage or prior to stabilization of the

oscillator. When V

exceeds the device V1

TRIP

Low V2MON Voltage Monitoring

The X5 5020 als o monitors a second voltage level and

asserts V2FAIL if t he volta ge falls below a preset mini-

mum V 2 TRIP . The V2FAIL signal is either ORed with

RESET to prevent the microprocessor from operating

in a power fail or brownout condition or used to inter-

rupt the microprocessor with no tiﬁcation of an impend-

ing power failure. The V2FAIL signal remains active

until the V2MON drops below 1V (V2MON falling). It

also remains active until V2MON returns and exceeds

V2 TRIP by 0.03V.

The V2MON voltage sensor is completely separate

from the operation of the low V CC sense, and is inde-

pendent of V CC supply.

Low V CC (V1MON) Voltage Monitoring

During operat ion, the X55020 monitors the V CC level

and asserts RESET/RESET if supply voltage falls

below a preset minimum V1 TRIP . During this t ime the

communication to the device is interrupted. The RESET/

RESET signal also prevents the microprocessor from

operating in a power fail or brownout condition. The

Figure 1. Two Uses of Dual Voltage Monitoring

V OUT

V2MON

V CC

X55020

Unregulated

Supply

Reg

V CC

System

Reset

Unregulated

Supply

Reg

V CC

RESET

V2M ON

V2FAIL

System

Interrupt

Reg

V2MO N

System

Reset

V2FAIL

Resistors selected so 3V appears on V2MON when

Unregulated supply reaches 6V.

Notice: No external components required to monitor

two voltages.

Watchdog Timer

The Watchdog Timer circuit mon itors the microproces-

sor activity by monit orin g the CS pin. The microproces-

sor must toggle the CS pin HIGH to LOW periodically

prior to the e xpiration of the watchdog time-out period

to prevent a RESET and RESET signal going active.

The state of two nonvolatile control bits in the Status

microprocessor can change these watchdog bits by

writing to the status register.

then V CC is applied to V OUT if V CC is or equal to or

greater than V BATT - 0.03V. When V CC drops to less

than V BATT - 0.03V, then V OUT is connected to V BATT

through an 80 Ohm (typical) switch. V OUT typically

supplies the system static RAM voltage, so the

switchover circuit operates to protect the contents of

the static RAM during a power failure. Typically, when

V CC has failed, the SRAMs go into a lower power state

and draw much less current than in their active mode.

When V CC returns, V OUT switches back to V CC when

V CC exceeds V BATT +0.03V. There is a 60mV hystere-

sis around this battery switch threshold to prevent

oscillations between supplies.

The Watchdog Timer oscillator stops when in battery

backup mode. It re-starts when V CC returns.

System Battery Switch

As long as V CC exceeds the low voltage detect thresh-

old V TRIP , V OUT is connected to V CC through a 5 Ohm

(typical) switch. When the V CC has fallen below V1 TRIP ,

While V CC is connected to V OUT the BATT-ON pin is

pulled LOW. The signal can drive an external PNP

transistor to provide additional current to the external

circuits during normal operation.

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Characteristics subject to change without notice.

5 of 22

value

for 150ms (nominal) the circuit releases RESET/

RESET, allowing the processor to begin executing code.

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