ZN427.PDF

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DS3006 - 2.1

ZN427E8 / ZN427J8

MICROPROCESSOR COMPATIBLE

8-BIT SUCCESSIVE APPROXIMATION A-D CONVERTER

The ZN427 is an 8-bit successive approximation converter

with three-state outputs to permit easy interfacing to a

common data bus. The IC contains a voltage switching DAC,

a fast comparator, successive approximation logic and a

2.56V precision bandgap reference, the use of which is pin

optional to retain flexibility. An external fixed or varying

reference may therefore be substituted, thus allowing

ratiometic operation

Only passive external components are required for

operation of the converter.

BUSY (END OF CONVERSION)

BIT 8 (LSB)

RD (OUTPUT ENABLE)

BIT 7

CLOCK

BIT 6

BIT 5

WR (START CONVERSION)

R EXT

BIT 4

V IN

BIT 3

FEATURES

V REF IN

BIT 2

Easy Interfacing to Microprocessor, or Operates as a

'Stand-Alone' Converter

V REF OUT

BIT 1 (MSB)

GROUND

+V CC (+5V)

Fast: 10 microseconds Conversion time Guaranteed

No Missing Codes over Operating Temperature Range

ZN427J8 (DC18)

ZN427E8 (DP18)

Data Outputs Three-State TTL Compatible, other

Logic Inputs and Output TTL and CMOS Compatible

Fig.1 Pin connection - top view

Choice of On-Chip or External Reference Voltage

Ratiometric Operation

ORDERING INFORMATION

Unipolar or Bipolar Input Ranges

Device type

Operating temperature

Package

Complementary to ZN428 DAC

ZN427E8

ZN427J8

0 ° C to +70 ° C

-55 ° C to +125 ° C

DP18

DC18

Commercial or Military Temperature Range

V REF OUT

D TO A OUTPUT

+2.5V

REFERENCE

R-2R LADDER

COMPARATOR

GROUND

ANALOGUE VOLTAGE SWITCHES

V IN

V REF IN

R EXT

SUCCESSIVE

APPROXIMATION REGISTER

WR (START CONVERSION)

CLOCK

INPUT

BUSY (END CONVERSION)

3-STATE BUFFERS

RD (OUTPUT ENABLE)

V CC

(+5V)

MSB

LSB

Fig.2 System diagram

ZN427

ABSOLUTE MAXIMUM RATINGS

Supply voltage V CC

+7.0V

Max. voltage, logic and V REF input

+V CC

Operating temperature range

0 ° C to +70 ° C (ZN427E8)

-55

C to +125

C (ZN427J8)

Storage temperature range

-55

C to +125

ELECTRICAL CHARACTERISTICS (at V CC = 5V, T amb = 25 ° C unless otherwise specified).

Parameter

Min.

Typ.

Max.

Units

Conditions

Converter

Resolution

Linearity error

Differential non-linearity

Linearity error T.C.

Differential non-linearity T.C.

Full-scale (gain) T.C.

Zero T.C.

Zero transition

2.545

± 0.5

2.555

Bits

LSB

ppm/ ° C

m V/ ° C

0.5

± 3

± 6

± 2.5

± 8

2.550

External Ref. 2.5V

00000000

to 00000001

DC Package

DP Package

V REF IN = 2.560V

F.S. transition

11111110

to 11111111

Conversion time

External reference voltage

Supply voltage (V CC )

Supply current

Power consumption

1.5

4.5

125

3.0

5.5

m s

See note 1

Comparator

Input current

Input resistance

Tail current, I EXT

Negative supply, V–

Input voltage

-3.0

-0.5

100

-30.0

3.5

m A

k W

m A

V IN = +3V, R EXT = 82k W

V - = -5V

See comparator (page x-xx)

Internal voltagee reference

Output voltage

Slope resistance

V REF temperature coefficient

Reference current

2.475

2.560

0.5

2.625

ppm/

R REF = 390

, C REF = 4

See reference (page x-xx)

Logic (over operating temperature range)

High level input voltage V IH

Low level input voltage V IL

High level input current,

WR and RD inputs I IH

High level input current,

Clock input I IH

Low level input current I IL

High level output current I OH

Low level output current I OL

High level output voltage V OH

Low level output voltage V OL

Disable output leakage

Input clamp diode voltage

Read input to data output

Enable/disable delay time t RD

Start pulse width tWR

WR to BUSY propagation delay t BD

Clock pulse width

Maximum clock frequency

2.0

2.4

250

500

900

180

160

1000

0.8

100

-5

-100

1.6

0.4

-1.5

250

m A

V IN = 5.5V, V CC = max.

V IN = 2.4V, V CC = max.

V IN = 5.5V, V CC = max.

V IN = 2.4V, V CC = max.

V IN = 0.4V, V CC = max.

kHz

I OH = max., V CC = min.

I OL = max., V CC = min.

V O = 2.4V

See Fig.9

See note 1

Note 1: A 900kHz clock gives a conversion time of 10 m s (9 clock periods).

m A

ZN427

GENERAL CIRCUIT OPERATION

The ZN427 utilises the successive approximation technique.

Upon receipt of a negative-going pulse at the WR input the

BUSY output goes low, the MSB is set to 1 and all other bits

are set to 0, which produces an output voltage of V REF/2 from the

DAC. This is compared to the input voltage V IN ; a decision is

made on the next negative clock edge to reset the

to 1. This procedure is repeated for all eight bits. On the ninth

negative clock edge BUSY goes high indicating that the

conversion is complete.

During a conversion the RD input will normally be held high to

keep the three-state buffers in their high impedance state.

Data can be read out by taking RD high, thus enabling the

three-state output. Readout is non-destructive. The BUSY

output may be tied to the RD input to automatically enable the

outputs when the data is valid.

MSB to 0 if > V IN or leave it set to 1 if < V IN .

V REF

Bit 2 is set to 1 on the same clock edge, producing an output

from the DAC of or + depending on the state

V REF

For reliable operation of the converter the start pulse applied

to the WR input must meet certain timing criteria with respect

to the converter clock. These are detailed in the timing

diagram of Fig.3.

of the MSB. This voltage is compared to V IN and on the next

clock edge a decision is made regarding bit 2, whilst bit 3 is set

Fig.3 Timing diagram

NOTES ON TIMING DIAGRAM

1. A conversion sequence is shown for the digital word

01100110. For clarity the three-state outputs are shown as

being enabled during the conversion, but normal practice

would be to disable them until the conversion was complete.

2. The BUSY output goes low during a conversion. When

BUSY goes high at the end of a conversion the output data is

valid. In a microprocessor system the BUSY output can be

used to generate an interrupt request when the conversion is

complete.

V REF

ZN427

3. In the timing diagram cross hatching indicates a 'don't

care' condition.

PRACTICAL CLOCK AND SYNCHRONISING

CIRCUITS

4. The start pulse operates as an asynchronous

(independent of clock) reset that sets the MSB output to 1 and

sets all other outputs and the end of conversion flag to 0. This

resetting occurs on the low-going edge of the start pulse and

as long as WR is low the converter is inhibited. Conversion

commences on the first active (negative going) clock edge

after the WR input has gone high again, when the MSB

decision is made. A number of timing constraints thus supply

to the start pulse.

The actual method of generating the clock signal and

synchronising it to the start conversion system in which the

ZN427 is incorporated.

P clock is used to drive the ZN427

and the m P write pulse meets the ZN427 timing criteria with

respect to the m P clock then generating the start pulse is

simply a matter of gating the decoded address with the

microprocessor write pulse. Whilst the conversion is being

performed the microprocesor can perform other instructions

or No operation (NOP). when the conversion is complete the

outputs can be enabled onto the bus by gating the decoded

address with the read pulse. A timing diagram for this

sequence of operation is given in Fig.4.

(a) The minimum duration of the start pulse is 250ns, to allow

reliable resetting of the converter logic circuits.

(b) There is no limit to the maximum duration of the start pulse.

between the negative going edge of the start pulse and the first

active clock edge that indicates the MSB desicion.

An advantage of using the microprocessor clock is that the

conversion time is known precisely in terms of machine

cycles. the data outputs may therefore be read after a fixed

delay of at least nine clock cycles after the end of the WR

pulse, when the conversion will be complete.

(d) To ensure relaible clocking the positive-going edge of the

start pulse should not occur within 200ns of an active

(negative-going) clock edge. The ideal place for the positive-

going edge of the start pulse is coincident with a positive-going

clock edge. As a special case of the above conditions that

start pulse may be synchronous with a negative-going clock

pulse.

Alternatively the read operation may be initiated by using the

BUSY output to generate interrupt request.

Fig.4 Typical timing diagram using m P clock and write pulse

In some systems, for example single-chip microcomputers

such as the 8048, this simple method may not be feasible for

one or more of the following reasons:

(a) The MPU clock is not available externally.

(b) The clock frequency is too high.

When used with a microprocessor the ZN427 can be treated

as RAM and can be assigned a memory address using an

address decoder. If the

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