DS14285_DS14287.pdf

DS14285/DS14287

Real Time Clock with NV RAM Control

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

Direct replacement for IBM AT computer

clock/calendar

V CCO

V CC

Functionally compatible with the

DS1285/DS1287

SQW

CEO

AD0

CEI

V BAT

IRQ

RESET

GND

R/W

AD1

Available as chip (DS14285, DS14285S, or

DS14285Q) or stand-alone module with

embedded lithium battery and crystal

(DS14287)

AD2

Automatic backup supply and write

protection to make external SRAM

nonvolatile

AD3

AD4

AD5

AD6

AD7

GND

DS14285 24-Pin DIP

DS14285S 24-Pin SOIC

Counts seconds, minutes, hours, days, day of

the week, date, month, and year with leap

year compensation valid up to 2100

Binary or BCD representation of time,

calendar, and alarm

12- or 24-hour clock with AM and PM in

12-hour mode

4 3 2 1 28 27 26

Daylight Savings Time option

AD0

AD1

AD2

AD3

AD4

AD5

CEI

V BAT

IRQ

RESET

GND

Multiplex bus for pin efficiency

Interfaced with software as 128 RAM

locations

– 14 bytes of clock and control registers

– 114 bytes of general purpose RAM

R/W

12 13 14 15 16 17 18

Programmable square wave outpu t sig nal

DS14285Q 28-Pin PLCC

Bus-compatible interrupt signals ( IRQ )

Three interrupts are separately software-

maskable and testable

– Time-of-day alarm once/second to

once/day

– Periodic rates from 122

V CCO

V CC

SQW

CEO

CEI

IRQ

RESET

R/W

s to 500 ms

– End of clock update cycle

AD0

AD1

AD2

Optional industrial temperature version

available DS14285 DIP, SOIC, and PLCC

AD3

AD4

AD5

AD6

AD7

GND

DS14287 24-Pin

Encapsulated Package

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080400

DS14285/DS14287

ORDERING INFORMATION

DS14285

RTC Chip; 24-pin DIP

DS14285N

RTC Chip; 24-pin DIP; Industrial Temp Range

DS14285S

RTC Chip; 24-pin SOIC

DS14285SN

RTC Chip; 24-pin SOIC; Industrial Temp Range

DS14285QN

RTC Chip; 28-pin PLCC; Industrial Temp Range

DS14287

RTC Module; 24-pin DIP

PIN DESCRIPTION

AD0-AD7

- Multiplexed Address/Data Bus

M OT

- Bus Type Select (DS14285Q only)

- Chip Select

A S

- Address Strobe

R/ W

- Read/Write Input

- Data Strobe

RES ET

- Reset Input

IRQ

- Interrupt Request Output

SQW

- Square Wave Output

GND

- +5V Supply

V CC O

- RAM Power Supply Output

CEI

- RAM Chip Enable In

CEO

- RAM Chip Enable Out

X1, X2

- 32.768 kHz Crystal Connections

V BAT

- +3V Battery Input

DESCRIPTION

The DS14285/DS14287 Real Time Clock with NVRAM Control provides the industry standard DS1287

clock function with the additional feature of providing nonvolatile control for an external SRAM.

Functions include a nonvolatile time-of-day clock, alarm, 100-year calendar, programmable interrupt,

square wave generator, and 114 bytes of nonvolatile static RAM. For the DS14287 a lithium energy

source, quartz crystal, and write protection circuitry are contained within a 24-pin dual in-line package.

The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external

energy source connected to the V BAT pin. A standard 32.768 kHz quartz crystal can be directly connected

to the DS14285 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load

capacitance (C L ) of 6 pF. For more information on crystal selection and crystal layout considerations,

please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.”

The DS14285/DS14287 uses its backup energy source and battery-backup controller to make a standard

CMOS static RAM nonvolatile during power-fail conditions. During power fail, the DS14285/DS14287

automatically write-protects the external SRAM and provides a V CC output sourced from its internal

battery.

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DS14285Q

RTC Chip; 28-pin PLCC

- No Connection

V CC

- Ground

DS14285/DS14287

For the DS14287 the internal lithium cell is electrically isolated from the clock and memory when

shipped from the factory. This isolation is removed after the first appli catio n of V CC, allowing the lithium

cell to provide data retention to the clock, internal RAM, V CCO and CEO on subsequent power-downs.

Care must be taken aft er th is isolation has been broken to avoid inadvertently discharging the lithium cell

through the V CCO and CEO pins.

OPERATION

The block diagram in Figure 1 shows the pin connections with the major internal functions of the

DS14285/DS14287. The following paragraphs describe the function of each pin.

SIGNAL DESCRIPTIONS

GND, V CC - DC power is provided to the device on these pins. V CC is the +5 volt input.

SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15

internal divider stages of the real time clock. The frequency of the SQW pin can be changed by

programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE

bit in Register B. The SQW signal is not available when V CC is less than 4.25 volts typical.

AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because

address information and data information time-share the same signal paths. The addresses are present

during the first portion of the bus cycle and the same pins and signal paths are used for data in the second

portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287

since the bus change from address to data occurs during the internal RAM access time. Addresses must be

valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address f rom

AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR

pul ses. In a read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or

RD pulses. The read cycle is terminated an d the bus returns to a high impedance state as DS transitions

low in the case of Motorola timing or as RD transitions high in the case of Intel timing.

MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When

connected to V CC , Motorola bus timing is selected. When connected to GND or left disconnected, Intel

bus timing is selected. The pin has an internal pull-down resistance of approximately 20 K

. This pin is

on the DS14285Q only.

AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The

falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287.

DS (Data Strobe or Read Input) - For the DS14285Q the DS/ RD pin has two modes of operation

depending on the level of the MOT pin. When the MOT pin is connected to V CC , Motorola bus timing is

selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data

Strobe. During read cycles, DS signifies the time that the DS14285Q is to drive the bidirectional bus. In

write cycles the trailing edge of DS causes the DS14285Q to latch the written data. Wh en th e MOT pin is

connected to GND, Intel bus timing is selected. In this mode the DS pin i s ca lled Read( RD ). RD identifies

the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition

as the Output Enable ( OE ) signal on a typical memory.

The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus

timing mode.

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DS14285/DS14287

R/ W (Read/Write Input) - The R/ W p in also has two modes of operation. When the MOT pin is

connected to V CC for Motorola timing, R/ W is at a level which i nd icates whether the current cycle is a

read or write. A r ea d cycle is indicated with a high level on R/ W while DS is high. A write cycle is

indicated when R/ W is low during DS.

Whe n the MOT pin is con ne cted to GND for Intel timing, the R/ W signal is an active l ow signal called

WR . In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic

RAMs.

CS (Chip Select Input) - The C hip Select signal must be asserted low for a bus cycle in the

DS14285/D S14 287 t o be accessed. CS must be kept in the active state during DS for Mo to rola timing

and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch

addresses but no access will occur. When V CC i s below 4.25 volts, the DS14285/DS14287 internally

inhibits access cycles by internally disabling the CS input. This action protects both the real time clock

data and RAM data during power outages.

IRQ (Interrupt Request Output) - The IRQ pin is an act ive low output of the DS14285/DS14287 that

can be used as an interrupt input to a processor. The IRQ output remains low as long as t he s tatus bit

causing the interrupt is present and the corresponding interru pt-enable bit is set. To clear the IRQ pin the

processor program normally reads the C register. The RESET pin also clears pending interrupts.

When no interrupt conditions are present , th e IRQ le vel is in the high impedance state. Multiple

interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an

external pull-up resistor.

RESET (Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the

RESET pin can be held low for a time in order to allow the power suppl y to sta bilize. The amount of time

that RESET is held low is dependent on the application. However, if RESET is used on power-up, the

time RESET is low should exceed 200 ms to make sure t hat the internal timer that controls the

DS14285/DS14287 on power-up has timed out. When RESET is low and V CC is above 4.25 volts, the

following occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to 0.

B. Alarm Interrupt Enable (AIE) bit is cleared to 0.

C. Update Ended Interrupt Flag (UF) bit is cleared to 0.

D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.

E. Periodic Interrupt Flag (PF) bit is cleared to 0.

F. The device is not accessible until RESET is returned high.

G. Alar m Interrupt Flag (AF) bit is cleared to 0.

H. IRQ pin is in the high impeda nce sta te.

I. Square Wave Output Enable ( SQWE ) bit is cleared to 0.

J. Upd ate Ended Interrupt Enable (UIE) is cleared to 0.

K. CEO is driven high.

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DS14285/DS14287

In a typical application RESET can be connected to V CC . This connection will allow the DS14287 to go in

and out of power fail without affecting any of the control registers.

CEI (E xte rnal RAM Chip Enable Input, active low) - CEI should be driven low to enable the external

RAM. CEI is internally pulled up with a 50k

CEO (External R A M Chip Enabl e Outp ut, active low) - When V CC is greater than 4.25 volts (typical),

CEO will reflect CEI provided the RESET is at a lo gic high. When V CC is less than 4.25 volts (typical),

CEO will be forced to an inactive level regardless of CEI .

V CCO (External RAM Power Supply Output) - V CCO provides the higher of V CC or V BAT through an

internal switch to power an external RAM.

DS14285 Only

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is

designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is

connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1

and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with

ground and that high frequency signals be kept away from the crystal area. For more information on

crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal

Considerations with Dallas Real Time Clocks.”

V BAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down

section for considerations in selecting the size of the external energy source

The battery should be connected directly to the V BAT pin. A diode must not be placed in series with the

battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current

protection circuitry is provided internal to the device and has passed the requirements of Underwriters

Laboratories for UL listing.

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resistor.

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