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The Low-Carb VHDL Tutorial
© Copyright: 2004 by Bryan Mealy (08-27-2004)
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Table of Contents
TABLE OF CONTENTS
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LIST OF FIGURES
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LIST OF TABLES
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LIST OF EXAMPLES
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1 INTENT AND PURPOSE
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2 INTRODUCTION
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3 VHDL INVARIANTS
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3.1 C ASE S ENSITIVITY
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3.2 W HITE S PACE
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3.3 C OMMENTS
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3.4 P ARENTHESIS
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3.5 VHDL S TATEMENTS
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3.6 IF , CASE , AND LOOP S TATEMENTS
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3.7 I DENTIFIERS
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3.8 R ESERVED W ORDS
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3.9 VHDL C ODING S TYLE
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4 BASIC VHDL DESIGN UNITS
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4.2 T HE A RCHITECTURE
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5 THE VHDL PROGRAMMING PARADIGM
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5.1 C ONCURRENT S TATEMENTS
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5.2 T HE S IGNAL A SSIGNMENT O PERATOR “<=”
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5.3 C ONCURRENT S IGNAL A SSIGNMENT S TATEMENTS
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5.4 C ONDITIONAL S IGNAL A SSIGNMENT
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5.5 S ELECTED S IGNAL A SSIGNMENT
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5.6 T HE P ROCESS S TATEMENT
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6 STANDARD ARCHITECTURES IN VHDL
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4.1 T HE E NTITY
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175171210.001.png
6.1 VHDL D ATAFLOW S TYLE A RCHITECTURE
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6.2 VHDL B EHAVIOR S TYLE A RCHITECTURE
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6.3 T HE P ROCESS S TATEMENT
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6.4 S EQUENTIAL S TATEMENTS
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6.4.1 S IGNAL A SSIGNMENT S TATEMENTS
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6.4.2 IF S TATEMENTS
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6.4.3 C ASE S TATEMENTS
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7 VHDL OPERATORS
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7.1 L OGICAL O PERATORS
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7.2 R ELATIONAL O PERATORS
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7.3 S HIFT O PERATORS
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7.4 A LL THE R EST OF THE O PERATORS
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7.4.1 T HE C ONCATENATION O PERATOR
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7.4.2 T HE M ODULUS AND R EMAINDER O PERATORS
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8 REVIEW
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9 USING VHDL FOR SEQUENTIAL CIRCUITS
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9.1 S IMPLE S TORAGE E LEMENTS U SING VHDL
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10 FINITE STATE MACHINE DESIGN USING VHDL
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10.1 O NE -H OT E NCODING FOR FSM S
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11 STRUCTURAL MODELING USING VHDL
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11.1 VHDL AND C OMPUTER P ROGRAMMING L ANGUAGES : E XPLOITING THE S IMILARITIES
12 DATA OBJECTS
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12.1 T YPES OF D ATA O BJECTS
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12.1.1 D ATA O BJECT D ECLARATIONS
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12.1.2 V ARIABLES AND THE A SSIGNMENT O PERATOR “ := ”
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12.1.3 S IGNALS VS . V ARIABLES
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12.2 D ATA T YPES
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12.2.1 C OMMONLY U SED T YPES
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12.2.2 I NTEGER T YPES
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12.2.3 T HE STD _ LOGIC T YPE
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13 LOOPING CONSTRUCTS
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13.1 FOR AND WHILE L OOPS
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13.1.1 FOR L OOPS
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13.2 L OOP C ONTROL : NEXT AND EXIT S TATEMENTS
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13.2.1 T HE NEXT S TATEMENT
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13.2.2 T HE EXIT S TATEMENT
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14 STANDARD DIGITAL CIRCUITS IN VHDL
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14.1 RET D F LIP - FLOP
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14.2 8-B IT R EGISTER WITH C HIP S ELECT
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14.3 S YNCHRONOUS UP / DOWN COUNTER ( WITH OTHER FEATURES )
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14.4 S HIFT R EGISTER WITH S YNCHRONOUS P ARALLEL L OAD
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14.5 8-B IT C OMPARATOR
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14.6 BCD TO 7-S EGMENT D ECODER
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14.7 4:1 M ULTIPLEXER
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14.8 3:8 D ECODER
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A APPENDIX : VHDL RESERVED WORDS
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13.1.2 WHILE L OOPS
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List of Figures
Figure 1: An example of VHDL case insensitivity........................................................... 10
Figure 2: An example showing VHDL's indifference to white space. ............................. 10
Figure 3: Two typical uses of comments. ......................................................................... 10
Figure 4: An example of parenthesis use that produces clarity. ....................................... 11
Figure 5: Generic form of an entity declaration................................................................ 14
Figure 6: Syntax of the port_clause. ................................................................................. 15
Figure 7: Example black box and associated VHDL entity declaration. .......................... 15
Figure 8: An example of an input and output diagram of a circuit and its associated
VHDL entity. ............................................................................................................ 16
Figure 9: A few examples of bus signals of varying content............................................ 16
Figure 10: A black box example containing busses and its associated entity declaration.17
Figure 11: Some common circuit that is well known to "execute" parallel operations. ... 20
Figure 12: VHDL code that describes the circuit of Figure 11......................................... 20
Figure 13: Algorithm code similar to the code in Figure 12............................................. 21
Figure 14: Syntax for the concurrent signal assignment statement. ................................. 22
Figure 15: Solution to EXAMPLE 1 .................................................................................. 22
Figure 16: Solution to EXAMPLE 2 .................................................................................. 24
Figure 17: Alternative but functionally equivalent architecture for EXAMPLE 2 ............ 24
Figure 18: Snytax for the conditional signal assignment statement. ................................ 25
Figure 19: Solution to EXAMPLE 3. ................................................................................. 26
Figure 20: Solution for EXAMPLE 4 : A 4:1 MUX using a conditional signal assignment
statement. .................................................................................................................. 27
Figure 21: Syntax for the selected signal assignment statement....................................... 28
Figure 22: Solution to EXAMPLE 5 .................................................................................. 28
Figure 23: Solution to EXAMPLE 6 .................................................................................. 29
Figure 24: Solution to EXAMPLE 7 .................................................................................. 30
Figure 25: Syntax for the process statement. .................................................................... 33
Figure 26: Entity declaration for circuit performing XOR function................................. 34
Figure 27: Dataflow and behavioral descriptions of my_xor_fun entity........................... 34
Figure 28: Syntax for the if statement............................................................................... 35
Figure 29: Solution to EXAMPLE 8 .................................................................................. 36
Figure 30: An alternate solution for EXAMPLE 8 . .......................................................... 37
Figure 31: Solution to EXAMPLE 9 .................................................................................. 37
Figure 32: Solution to EXAMPLE 10 ................................................................................ 38
Figure 33: Syntax for the case statement. ......................................................................... 39
Figure 34: Solution to EXAMPLE 11 ................................................................................ 40
Figure 35: Solution to EXAMPLE 12 ................................................................................ 41
Figure 36: Examples of the concatenation operator. ........................................................ 44
Figure 37: Solution to EXAMPLE 13 ................................................................................ 49
Figure 38: Solution to EXAMPLE 14 ................................................................................ 50
Figure 39: Solution to EXAMPLE 15 ................................................................................ 51
Figure 40: Block diagram for a Moore-type FSM. ........................................................... 53
Figure 41: Model for VHDL implementations of FSMs. ................................................. 54
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