G02-AppendixA.pdf
(
230 KB
)
Pobierz
175182192 UNPDF
April 26, 1999 11:53 g02-appa
Sheet number 1 Page number 685 black
appendix
A
VHDL REFERENCE
a
b
c
d
e
f
g
h
8
7
6
5
4
3
2
1
12. a2–a4, Bc8–b7
685
April 26, 1999 11:53
g02-appa
Sheet number 2 Page number 686 black
686
APPENDIX A
VHDL REFERENCE
This appendix describes the features of VHDL that are used in this book. It is meant to
serve as a convenient reference for the reader. Hence only brief descriptions are provided,
along with examples. The reader is encouraged to first study the introduction to VHDL in
sections 2.9 and 4.12.5.
Another useful source of information on VHDL is the MAX+plusII CAD system that
accompanies the book. The on-line help included with the software describes how to use
VHDL with MAX+plusII, and the “templates” provided with the Text Editor tool are a
convenient guide to VHDL syntax. We describe how to access these features of the CAD
tools in Appendix B.
In some ways VHDL uses an unusual syntax for describing logic circuits. The prime
reason is that VHDL was originally intended to be a language for documenting and simu-
lating circuits, rather than for describing circuits for synthesis. This appendix is not meant
to be a comprehensive VHDL manual. While we discuss almost all the features of VHDL
that are useful in the synthesis of logic circuits, we do not discuss any of the features that are
useful only for simulation of circuits or for other purposes. Although the omitted features
are not needed for any of the examples used in this book, a reader who wishes to learn more
about using VHDL can refer to specialized books [1–7].
How
Not
to Write VHDL Code
In section 2.9 we mentioned the most common problem encountered by designers who
are just beginning to write VHDL code. The tendency for the novice is to write code
that resembles a computer program, containing many variables and loops. It is difficult
to determine what logic circuit the CAD tools will produce when synthesizing such code.
This book contains more than 100 examples of complete VHDL code that represents a wide
range of logic circuits. In all of these examples, the code is easily related to the described
logic circuit. The reader is encouraged to adopt the same style of code. A good general
guideline is to assume that if the designer cannot readily determine what logic circuit is
described by the VHDL code, then the CAD tools are not likely to synthesize the circuit
that the designer is trying to describe.
Since VHDL is a complex language, errors in syntax and usage are quite common.
Some problems encountered by our students, as novice designers, are listed at the end of
this appendix in section A.11. The reader may find it useful to examine these errors in an
effort to avoid them when writing code.
Once complete VHDL code is written for a particular design, it is useful to analyze the
resulting circuit synthesized by the CAD tools. Much can be learned about VHDL, logic
circuits, and logic synthesis by studying the circuits that are produced automatically by the
CAD tools.
A.1
DOCUMENTATION IN VHDL CODE
Documentation can be included in VHDL code by writing a comment. The two characters
‘-’, ‘-’ denote the beginning of the comment. The VHDL compiler ignores any text on a
line after the ‘- -’.
April 26, 1999 11:53 g02-appa
Sheet number 3 Page number 687 black
A.2
DATA OBJECTS
687
Example A.1
- - this is a VHDL comment
A.2
DATA OBJECTS
Information is represented in VHDL code as data objects. Three kinds of data objects
are provided: signals, constants, and variables. For describing logic circuits, the most
important data objects are signals. They represent the logic signals (wires) in the circuit.
The constants and variables are also sometimes useful for describing logic circuits, but they
are used infrequently.
A.2.1
DATA OBJECT NAMES
The rules for specifying data object names are simple: any alphanumeric character may
be used in the name, as well as the ‘_’ underscore character. There are four caveats. A
name cannot be a VHDL keyword, it must begin with a letter, it cannot end with an ‘_’
underscore, and it cannot have two successive ‘_’ underscores. Thus examples of legal
names are
x
,
x
1,
x
_
y
, and
Byte
. Some examples of illegal names are 1
x
,_
y
,
x
__
y
, and
entity
. The latter name is not allowed because it is a VHDL keyword. We should note that
VHDL is not case sensitive. Hence x is the same as X, and ENTITY is the same as entity.
To make the examples of VHDL code in this book more readable, we use uppercase letters
in all keywords.
To avoid confusion when using the word signal, which can mean either a VHDL data
object or a logic signal in a circuit, we sometimes write the VHDL data object as SIGNAL.
A.2.2
DATA OBJECT VALUES AND NUMBERS
We use SIGNAL data objects to represent individual logic signals in a circuit, multiple logic
signals, and binary numbers (integers). The value of an individual SIGNAL is specified
using apostrophes, as in ’0’ or ’1’. The value of a multibit SIGNAL is given with double
quotes. An example of a four-bit SIGNAL value is "1001", and an eight-bit value is
"10011000". Double quotes can also be used to denote a binary number. Hence while
"1001" can represent the four SIGNAL values ’1’, ’0’, ’0’, ’1’, it can also mean the integer
.
1001
/
2
D
A.2.3
SIGNAL DATA OBJECTS
SIGNAL data objects represent the logic signals, or wires, in a circuit. There are three
places in which signals can be declared in VHDL code: in an entity declaration (see section
.
9
/
10
. Integers can alternatively be specified in decimal by not using quotes, as
in 9 or 152. The values of CONSTANT or VARIABLE data objects are specified in the
same way as for SIGNAL data objects.
April 26, 1999 11:53
g02-appa
Sheet number 4 Page number 688 black
688
APPENDIX A
VHDL REFERENCE
A.4.1), in the declarative section of an architecture (see section A.4.2), and in the declarative
section of a package (see section A.5). A signal has to be declared with an associated
type
,
as follows:
SIGNAL signal_name : type_name ;
The signal’s
type_name
determines the legal values that the signal can have and its legal
uses in VHDL code. In this section we describe 10 signal types: BIT, BIT_VECTOR,
STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, SIGNED, UNSIGNED, INTE-
GER, ENUMERATION, and BOOLEAN.
A.2.4
BIT AND BIT_VECTOR TYPES
These types are predefined in the VHDL Standards IEEE 1076 and IEEE 1164. Hence no
library is needed to use these types in the code. Objects of BIT type can have the values
’0’ or ’1’. An object of BIT_VECTOR type is a linear array of BIT objects.
Example A.2
SIGNAL x1 : BIT ;
SIGNAL C : BIT_VECTOR (1 TO 4) ;
SIGNAL Byte : BIT_VECTOR (7 DOWNTO 0) ;
The signals
C
and
Byte
illustrate the two possible ways of defining a multibit data object.
The syntax “lowest_index TO highest_index” is useful for a multibit signal that is simply
an array of bits. In the signal
C
the most-significant (left-most) bit is referenced using
lowest_index, and the least-significant (right-most) bit is referenced using highest_index.
The syntax “highest_index DOWNTO lowest_index” is useful if the signal represents a
binary number. In this case the most-significant (left-most) bit has the index highest_index,
and the least-significant (right-most) bit has the index lowest_index.
The multibit signal
C
represents four BIT objects. It can be used as a single four-bit
quantity, or each bit can be referred to individually. The syntax for referring to the signals
individually is
C
(1),
C
(2),
C
(3), or
C
(4). An assignment statement such as
C
<
= "1010" ;
results in
C
(1)
D
1,
C
(2)
D
0,
C
(3)
D
1, and
C
(4)
D
0.
The signal
Byte
comprises eight BIT objects. The assignment statement
Byte
<
= "10011000" ;
results in
Byte.
7
/
=1,
Byte.
6
/
= 0, and so on to
Byte.
0
/
=0.
A.2.5
STD_LOGIC AND STD_LOGIC_VECTOR TYPES
The STD_LOGIC type was added to the VHDL Standard in IEEE 1164. It provides more
flexibility than the BIT type. To use this type, we must include the two statements
April 26, 1999 11:53 g02-appa
Sheet number 5 Page number 689 black
A.2
DATA OBJECTS
689
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
These statements provide access to the
std_logic_1164
package, which defines the
STD_LOGIC type. We describe VHDL packages in section A.5. In general, they are
used as a place to store VHDL code, such as the code that defines a type, which can then
be used in other source code files. The following values are legal for a STD_LOGIC data
object: 0, 1, Z,
−
stands for “don’t care.” The value
L stands for “weak 0,” H means “weak 1,” U means “uninitialized,” X means “unknown,”
and W means “weak unknown.” The STD_LOGIC_VECTOR type represents an array of
STD_LOGIC objects.
−
Example A.3
SIGNAL x1, x2, Cin, Cout, Sel : STD_LOGIC ;
SIGNAL C
: STD_LOGIC_VECTOR (1 TO 4) ;
SIGNAL X, Y, S
: STD_LOGIC_VECTOR (3 DOWNTO 0) ;
STD_LOGIC objects are often used in logic expressions in VHDL code.
STD_LOGIC_VECTOR signals can be used as binary numbers in arithmetic circuits by
including in the code the statement
USE ieee.std_logic_signed.all ;
The
std_logic_signed
package specifies that it is legal to use the STD_LOGIC_VECTOR
signals with arithmetic operators, like + (see section A.7.1). The VHDL compiler should
generate a circuit that works for signed numbers. An alternative is to use the package
std_logic_unsigned
. In this case the compiler should generate a circuit that works for
unsigned numbers.
A.2.6
STD_ULOGIC TYPE
In this book we use the STD_LOGIC type in most examples of VHDL code. This type
is actually a
subtype
of the STD_ULOGIC type. Signals that have the STD_ULOGIC
type can take the same values as the STD_LOGIC signals that we have been using. The
only difference between STD_ULOGIC and STD_LOGIC has to do with the concept of
a
resolution function
. In VHDL a resolution function is used to determine what value a
signal should take if there are two sources for that signal. For example, two tri-state buffers
could both have their outputs connected to a signal,
x
. At some given time one buffer might
produce the output value ’Z’ and the other buffer might produce the value 1. A resolution
function is used to determine that the value of
x
should be 1 in this case. The STD_LOGIC
type allows multiple sources for a signal; it resolves the correct value using a resolution
function that is provided as part of the
std_logic_1164
package. The STD_ULOGIC type
, L, H, U, X, and W. Only the first four are useful for synthesis of logic
circuits. The value Z represents high impedance, and
Plik z chomika:
f_e_a_r_
Inne pliki z tego folderu:
VII.1.pdf
(560 KB)
vhdl_example.pdf
(10 KB)
Randomization-V1.pdf
(175 KB)
Accellera_VHDL_4_0_022008(1).pdf
(42 KB)
Welcome to the VHDL Language.pdf
(1241 KB)
Inne foldery tego chomika:
Artykuły, poradniki
Bascom AVR
c++
Dokumenty
Eagle
Zgłoś jeśli
naruszono regulamin