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KD-LX333R
SERVICE MANUAL
CD RECEIVER
KD-LX333R
KD-LX333R
ATT
SOURCE
OFF
S
T
D
M
7
1 0
1 1
1 2
Area Suffix
E
EX
Continental Europe
Central Europe
Contents
Safety precaution
Preventing static electricity
Disassembly method
Adjustment method
1-2
1-3
1-4
1-13
Flow of finctional operation intil opelation
until TOC read
Maintenance of laser pickup
Replacement of laser pickup
Description of Major ICs
1-14
1-16
1-16
1-17~33
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
No.49715
Jun. 2002
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KD-LX333R
Description of major ICs
TC9490FA (IC521) : DSP & DAC
1.Pin layout & Block daiagram
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DV SS3
49
32
TEZI
RO
50
Clock
generator
PWM
31
TEI
D/A
DV DD3
51
LPF
30
SBAD
DVR
52
1-bit
DAC
29
FEI
Servo control
A/D
LO
53
28
RFRP
DV SS3
54
27
RFZI
ZDET
55
Address
circuit
ROM
Digital equalizer
automatic
adjustment circuit
26
RFCT
V SS5
56
RAM
25
AV DD3
BUS0
57
24
RFI
Data
slicer
CLV servo
BUS1
58
16k
RAM
23
SLCO
BUS2
59
Sync signal
protection
EFM
22
AV SS3
BUS3
60
VCO
21
VCOF
BUCK
61
Audio output
circuit
Digital output
20
RV REF
/CCE
62
Micro-
controller
interface
Sub code
detector
PLL
TMAX
19
LPFO
/RST
63
18
LPFN
V DD5
64
17
TMAX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1-17
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KD-LX333R
2.Pin function (1/2)
TC9490FA(2/3)
Pin No.
1
2
Symbol
BCK
LRCK
I/O
O
O
Function
Bit clock outputpin 32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin."L" for L channe and "H" for R channel.
Output polarity can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by command.
Digital data output pin. Outputs up to double-speed playback.
Correction flag output pin.When set to "H",AOUT output cannot be corrected
by C2 correction processing.
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin."H" level when result is OK.
Subcode P-W data read clockI/O pin. I/O polarity selectable by command.
Subcode P-W data output pin.
Playback frame sync signal output pin.
Subcode block sync signal output pin. "H" level at S1 when subcode sync is
detected.
Playback speed mode flag output pins.
3
4
5
AOUT
DOUT
IPF
O
O
O
6
7
8
9
10
11
12
VDD3
VSS3
SBOK
CLCK
DATA
SFSY
SBSY
-
-
O
I/O
O
O
O
13
/HSO
O
/UHSO /HSO
Playback speed
14
/UHSO
O
H
H
L
--
H
L
L
--
Normal
Double
4 times
---
15
16
17
PVDD3
PDO
TMAX
-
O
O
PLL-only 3.3V power supply voltage pin.
EFM and PLCK phase difference signal output pin.
TMAX detection result output pin.
TMAX Detection result
TMAX Output
Longer than fixed period
Within fixed period
Shorter than fixed period
"PV DD3 "
"HIZ"
"AV SS3"
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
LPFN
LPFO
PVREF
VCOF
AV SS3
SLCO
RFI
AV
RFCT
RFZI
RFRP
FEI
SBAD
TEI
TEZI
FOO
TRO
V REF
I
O
-
O
-
O
I
-
I
I
I
I
I
I
I
O
O
-
Inverted input pin for PLL LPF amp.
Output oin for PLL LPF amp.
PLL-only V REF pin.
VCO filter pin.
Analog GND pin.
DAC output pin for data slice level generation.
RF signal input pin.Zin selectable by command.
Analog 3.3V power supply voltage pin.
RFRP signal center level input pin.
RFRP signal zero-cross input pin.
RF ripple signal input pin.
Focus error signal input pin.
Sub-beam adder signal input pin.
Tracking error input pin. Inputs when tracking servo is on.
Tracking error signal zero-cross input pin.
Focus equalizer output pin.
Tracking equalizer output pin.
Analog reference power supply voltage pin.
1-18
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KD-LX333R
2.Pin function (2/2)
TC9490FA(3/3)
Pin No.
36
37
38
Symbol
RFGC
TEBC
SEL
I/O
O
O
O
Function
RF amplitude adjustment control signal output pin.
Tracking balance control signal output pin.
APC circuit ON/OFF signal output pin. At laser on,high impedance with
UHS="L" ,H output with UHS="H".
Analog 3.3V power supply voltage pin.
Feed equalizer output pin.
Disc equalizer output pin.
Digital GND pin.
Digital 3.3V power supply voltage pin.
Test input pin. Normally,fixed to "L".
System clock oscillator GND pin.
System clock oscilatoe input pin.
System clock oscillator output pin.
System clock oscillator 3.3V power supply voltage pin.
DA converter GND pin.
R-channel data forward output pin.
DA converter 3.3V power supply pin.
Reference voltage pin.
L-channel data forward output pin.
DA converter GND pin.
1 bit DA converter zero data detection flag output pin.
Microcontroller interface GND pin.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
AV DD3
FMO
DMO
V SS3
V DD3
TESIN
XV SS3
XI
XO
XV DD3
DV SS3
RO
DV DD3
DVR
LO
DV SS3
ZDET
V SS5
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
-
O
O
-
-
I
-
I
O
-
-
O
-
-
O
-
O
-
I/O
Microcontroller interface data I/O pins.
I
I
Microcontroller interface clock input pin.
Microcontroller interface chip enable signal input pin.At "L".
Bus0 to BUS3 are active.
Reset signal input pin. At reset,"L".
Microcontroller interface 5V power supply pin.
63
64
/RST
V DD5
I
-
NJM4565MD (IC151,IC171,IC323) : Operational amp
A OUTPUT
1
8
V +
A INPUT
2
7
B OUTPUT
A INPUT
3
6
B INPUT
V -
4
5
B INPUT
1-19
-
+
-
+
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KD-LX333R
TA2147F-X (IC501) : RF amp.
1.Terminal layout
2.Block diagram
GVSW
13
20k 20k
PEAK
12 RFDC
50k
15k
VRO
14
20 A
11
TEO
40k
20k
FEO
15
10
TEN
20k
15k
20k
FEN
16
50 A
9
TEBC
20k
12k
2k
50k
RFRP
17
8
SEL
12k
20k
RFRPIN
18
BOTTOM
PEAK
1k
7
LDO
14k
2k
RFGO
19
6
MDI
1.75k
240k
15pF
x0.5
RFGC
20
k
x2
5
TNI
20k
240k
15pF
x0.5
AGCIN
21
1
x2
4
TPI
80k
RFO
22
60k
20k
3
FPI
180k
60k
80k
RFN
23
40pF
20k
2
FNI
3k
GND
24
3k
1
Vcc
1-20
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