WistronKAI-DV2000.pdf
(
1250 KB
)
Pobierz
5
4
3
2
1
KAI Block Diagram
SYSTEM DC/DC
TPS51120
Project code : 91.4F601.001
PCB P/N : 05233
Revision : SA
INPUTS
OUTPUTS
Intel CPU
5V_S5
DCBATOUT
3V_S5
CLK GEN
D
D
Yonah/Merom
ICS954305
SYSTEM DC/DC
GDDR3 32MB
4,5
3
41
MAX8743
CRT
RGB CRT
13
INPUTS
OUTPUTS
Host BUS
533/667MHz
1D05V_S0
LCD
DCBATOUT
1D8V_S3
LVDS
14
DDRII
533/667
Slot 0
nVIDIA
G72M-V G3-64
DDRII 667 Channel A
Calistoga
PM
11
TVOUT
SVIDEO
MAXIM CHARGER
13
DDRII
533/667
Slot 1
DDR II 667 Channel B
PCIE x 16
MAX8725
38,39,40
11
6,7,8,9,10
INPUTS
OUTPUTS
BT+
1394
1394
C
DMI I/F
100MHz
C
18V 3.0A
Ricoh
R5C832
23
DCBATOUT
CAMERA
30
5V 100mA
SD/SDIO/MMC
MS/MS Pro/xD
PCI
CardReader
BLUE
TOOTH
23
22,23
CPU DC/DC
30
MAX8736ETL
USB x 3
USB 2.0
21
INPUTS
OUTPUTS
ICH7-M
RJ45
CONN
10/100 NIC
VCC_CORE
LCI
Intel 82562
SATA
HDD
DCBATOUT
0.844~1.3V
44A
26
25
20
ODD
PATA
20
PCB LAYER
B
RJ11
CONN
MODEM
B
HD Audio
AMOM
WAKIKI
LPC Bus
L1:
Signal 1
15,16,17,18
INTERNAL
ARRAY MIC
L2:
GND
L3:
Signal 2
MIC IN
AUDIO CODEC
L4:
Signal 3
PCIE+USB 2.0
KBC
LINE OUT
ENE KB3910SF
L5:
VCC
Signal 4
27
Ricoh
R5538
29
L6:
SPDIF
26
L7:
L8:
GND
Signal 5
Flash ROM
1MB
OP AMP
Thermal
& Fan
31
Mini-Card
Mini-Card
Capacity
Button
Touch
Pad
Int.
KB
APA2031
New Card
CIR
28
802.11a/b/g
<Core Design>
<Core Design>
<Core Design>
A
A
26
24
24
30
30
30
G792
19
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH
SPEAKER
DOCK
10/100
Ethernet
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
CRT
MIC IN
LINE OUT
S/PDIF
TVOUT
CIR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
15
A3
A3
A3
KAI
KAI
KAI
SA
SA
SA
Date:
Date:
Date:
Thursday, November 24, 2005
Thursday, November 24, 2005
Thursday, November 24, 2005
Sheet
Sheet
Sheet
1
1
1
of
of
of
44
44
44
5
4
3
2
1
A
B
C
D
E
Calistoga Strapping Signals and
Configuration
125CV Spread Spectrum Select
ICH7M Integrated Pull-up
and Pull-down Resistors
page 7
page 3
ICH6-M EDS 14308 0.8V1
Pin Name
Strap Description
Configuration
SS3
SS2
SS1
SS0
Spread Amount%
ACZ_BIT_CLK,
DPRSLP#, EE_DIN,
CFG[2:0]
FSB Frequency Select
001 = FSB533
011 = FSB667
0
0
0
0
1
-0.8
-1.0
-1.25
-1.5
-1.75
-2.0
-2.5
-3.0
EE_DOUT,
GNT[5]#/GPO[17],
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
others = Reserved
0
0
0
ICH6 internal 20K pull-ups
LDRQ[1]/GPI[41],
4
4
CFG[4:3]
Reserved
0
0
0
1
1
0
0 = DMI x2
0
1
CFG5
DMI x2 Select
(Default)
1 = DMI x4
PME#, PWRBTN#,
TP[3]
0
0
0
0
1
1
0
0
CFG6
0=Moby Dick
1=Calistoga
0
1
LAN_RXD[2:0]
ICH6 internal 10K pull-ups
0 = Reserved
1 =Mobile CPU(Default)
1
1
1
0
CFG7
CPU Strap
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
ICH6 internal 20K pull-downs
1
1
CFG8
Reserved
DPRSLPVR,
1
0
0
0
+-0.3
+-0.4
+-0.5
+-0.6
+-0.8
0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order
SPKR,
EE_CS,
CFG9
PCI Express Graphics
Lane Reversal
1
0
0
1
1
0
1
0
USB[7:0][P,N]
ICH6 internal 15K pull-downs
CFG[11:10]
Reserved
1
0
1
1
CFG[13:12]
Reserved
DD[7],
SDDREQ
ICH6 internal 11.5K pull-downs
1
1
0
0
CFG[15:14]
Reserved
1
1
1
1
0
1
+-1.0
+-1.25
+-1.5
LAN_CLK
ICH6 internal 100K pull-downs
CFG16
FSB Dynamic ODT
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
1
0
(Default)
CFG17
Global R-comp Disable
(All R-comps)
0 = All R-comp Disable
1 = Normal Operation (Default)
1
1
1
1
ICH7M IDE Integrated Series
Termination Resistors
3
CFG18
VCC Select
(Default)
3
0 = 1.05V
1 = 1.5V
PCI Routing
CFG19
DMI Lane Reversal
0 = Normal operation (Default):lane
Numbered in order
DD[15:0],
DDACK#,
DIOW#,
DIOR#, DREQ,
1 =Reverse Lane,4->0,3->1 ect...
0 = Only SDVO or PCIE x1 is
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
IDSEL
IRQ
REQ/GNT
approximately 33 ohm
IORDY,
DA[2:0],
DCS1#,
CFG20
SDVO/PCIE
Concurrent
R5C832
25
0
DCS3#,
IDEIRQ
SDVOCRTL
SDVO Present
0 = No SDVO device present
(Default)
_DATA
1= SDVO device present
NOTE:
All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
ITP Debug Conn.
1D05V_S0
History
11.18.2004: mini card not ready
2
2
R72
54D9R2F-L1-GP
R66
39D2R2F-L-GP
R68
54D9R2F-L1-GP
CN1
CN1
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
4
XDP_TDI
4
XDP_TMS
4
XDP_TRST#
4
XDP_TCK
R69
R69
22D6R2F-L1-GP
22D6R2F-L1-GP
DY
DY
TDO_FLEX#
1
2
4
XDP_TDO
CLK_XDP#
CLK_XDP
3
CLK_XDP#
3
CLK_XDP
XDP_TCK
1
DY
DY
2
RESET_FLEX#
4,6
H_CPURST#
R71
R71
22D6R2F-L1-GP
22D6R2F-L1-GP
4
XDP_BPM#5
4
XDP_BPM#4
R67
680R2J-3-GP
R70
27D4R2F-L1-GP
3D3V_S0
4
XDP_BPM#0
4
XDP_BPM#1
R73
220R2J-L2-GP
4
XDP_BPM#2
<Core Design>
<Core Design>
<Core Design>
1
1
4
XDP_BPM#3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
4,17
XDP_DBRESET#
1D05V_S0
DY
DY
C105
SCD1U16V2ZY-2GP
DY
Title
Title
Title
MLX-CON28-U
MLX-CON28-U
ITP
ITP
ITP
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
KAI
KAI
KAI
SA
SA
SA
Date:
Date:
Date:
Monday, November 28, 2005
Monday, November 28, 2005
Monday, November 28, 2005
Sheet
Sheet
Sheet
2
2
2
of
of
of
44
44
44
A
B
C
D
E
A
B
C
D
E
3D3V_S0
3D3V_S0
3D3V_S0
3D
3V_APWR_S0
3D3V_48MPWR_S0
3D3V_CLKGEN_S0
1
2
1
2
1
2
R439
R439
0R3-0-U-GP
0R3-0-U-GP
R171
R171
0R3-0-U-GP
0R3-0-U-GP
R172
R172
0R3-0-U-GP
0R3-0-U-GP
C555
C555
C334
SC4D7U10V5ZY-3GP
C333
SCD1U16V2ZY-2GP
C331
SC4D7U10V5ZY-3GP
C332
SCD1U16V2ZY-2GP
C351
SC10U10V5ZY-1GP
C554
SCD1U16V2ZY-2GP
C310
SCD1U16V2ZY-2GP
C557
SCD1U16V2ZY-2GP
C312
SCD1U16V2ZY-2GP
C556
SCD1U16V2ZY-2GP
C553
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
4
4
IN
(3D3V_S0)
EN
(6218_PGOOD)
L
H
OUT
(VTT_PWRGD#)
H
PCLK_FWH_1
33R2J-2-GP
33R2J-2-GP
R435
R435
2
1
PCLK_FWH
31
H
R146
10KR2J-3-GP
R149
10KR2J-3-GP
PCLK_PCM_1
SS_SEL
2
1
PCLK_PCM
22
33R2J-2-GP
33R2J-2-GP
R434
R434
PCLK_KBC_1
2
1
PCLK_KBC
29
33R2J-2-GP
33R2J-2-GP
R432
R432
H/L : CPU_ITP/SRC10
X
Hi - Z
3D3V_48MPWR_S0
3D3V_APWR_S0
1016
ITP_EN
FSA
SS_SEL
3D3V_CLKGEN_S0
CPU_SEL2_1
CPU_SEL2
1
2
H/L: 27MHz/96MHz
CPU_SEL1
R546
R546
2K2R2J-2-GP
2K2R2J-2-GP
PM_STPCPU#
17
R148
10KR2J-3-GP
DY
R147
10KR2J-3-GP
DY
CLK_CPU_BCLK_1
1
2
4
CLK_EN#
34
CLK_CPU_BCLK
4
CLK_CPU_BCLK_1#
3
CLK_CPU_BCLK#
4
RN25
RN25
SRN33J-5-GP-U
SRN33J-5-GP-U
U24
U24
CLK_MCH_BCLK_1
1
2
4
CLK_MCH_BCLK
6
CPU_SEL0
CLK_MCH_BCLK_1#
2
1
3
CLK_MCH_BCLK#
6
2K2R2J-2-GP
2K2R2J-2-GP
R426
R426
RN23
RN23
SRN33J-5-GP-U
SRN33J-5-GP-U
R423
R423
33R2J-2-GP
33R2J-2-GP
FSA
2
1
17
CLK48_ICH
PEG_REFCLKP_1
2
3
4
PEG_REFCLKP
38
3D3V_S0
PEG_REFCLKN_1
1
PEG_REFCLKN
38
RN22
RN22
SRN33J-5-GP-U
SRN33J-5-GP-U
CLK_PCIE_NEW_1
CLK_PCIE_NEW_1#
2
3
4
CLK_PCIE_NEW
26
1
2
CLKREQ1#
46
50
PEG_REFCLKP_1
1
CLK_PCIE_NEW#
26
CLKREQ1#
SRCT1
R169
10KR2J-3-GP
R430
R430
1
DY
DY
2
1KR2J-1-GP
1KR2J-1-GP
CLKREQ2#
CLKREQ3#
CLKREQ4#
CLKREQ6#
CLKREQ7#
CLKREQ8#
26
52
CLK_PCIE_NEW_1
RN21
RN21
SRN33J-5-GP-U
SRN33J-5-GP-U
CLKREQ2#
SRCT2
3
R170
R170
1KR2J-1-GP
1KR2J-1-GP
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#
3
1
2
28
55
2
3
4
CLK_MCH_3GPLL
7
CLKREQ3#
SRCT3
R153
R153
1KR2J-1-GP
1KR2J-1-GP
CLK_PCIE_SATA_1
1
2
57
58
1
CLK_MCH_3GPLL#
7
CLKREQ4#
SRCT4
CLKREQ2#
R431
R431
1KR2J-1-GP
1KR2J-1-GP
CLKREQ5#
CLK_PCIE_ICH_1
RN28
RN28
SRN33J-5-GP-U
SRN33J-5-GP-U
1
2
1
2
29
60
26
CONN_CLKREQ#
CLKREQ5#
SRCT5
R168
R168
0R2J-2-GP
0R2J-2-GP
R152
R152
1KR2J-1-GP
1KR2J-1-GP
CLK_PCIE_SATA_1
1
2
62
63
2
3
4
CLK_PCIE_SATA
16
CLKREQ6#
SRCT6
R433
R433
1KR2J-1-GP
1KR2J-1-GP
CLK_PCIE_MINI1_1
CLK_PCIE_SATA_1#
1
2
38
66
1
CLK_PCIE_SATA#
16
CLKREQ7#
SRCT7
R150
R150
1KR2J-1-GP
1KR2J-1-GP
CLK_PCIE_MINI2_1
RN29
RN29
SRN33J-5-GP-U
SRN33J-5-GP-U
1
2
71
70
CLKREQ8#
SRCT8
R437
R437
1KR2J-1-GP
1KR2J-1-GP
CLKREQ9#
CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#
1
2
72
3
2
3
4
CLK_PCIE_ICH
17
CLKREQ9#
SRCT9
R190
R190
1KR2J-1-GP
1KR2J-1-GP
1
CLK_PCIE_ICH#
17
RN30
RN30
SRN33J-5-GP-U
SRN33J-5-GP-U
PEG_REFCLKN_1
47
51
LCD100/96/SRC0_T
SRCC1
CLK_PCIE_NEW_1#
48
53
LCD100/96/SRCO_C
SRCC2
CLK_MCH_3GPLL_1#
56
SRCC3
CLK_PCIE_SATA_1#
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#
CLK_PCIE_MINI2_1
CLK_PCIE_MINI2_1#
59
2
3
4
CLK_PCIE_MINI1
24
SRCC4
VGA_27MHZ_1
VGA_27MHZSS_1
CLK_PCIE_ICH_1#
2
1
43
61
1
40
VGA_27MHZ
CLK_PCIE_MINI1#
24
DOTT_96MHZ/27MHZ_NONSPREAD
SRCC5
33R2J-2-GP
33R2J-2-GP
R4
28
R428
RN32
RN32
SRN33J-5-GP-U
SRN33J-5-GP-U
2
1
44
64
40
VGA_27MHZSS
DOTC_96MHZ/27MHZ_SPREAD
SRCC6
33R2J-2-GP
33R2J-2-GP
R429
R429
CLK_PCIE_MINI1_1#
67
1
2
4
CLK_PCIE_MINI2
24
SRCC7
CLK_PCIE_MINI2_1#
69
3
CLK_PCIE_MINI2#
24
SRCC8
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
GEN_XTAL_IN
GEN_XTAL_OUT
RN33
RN33
SRN33J-5-GP-U
SRN33J-5-GP-U
1
2
20
2
X1
SRCC9
C311
C311
GEN_XTAL_OUT_R
1
2
19
X2
R156
R156
0R2J-2-GP
0R2J-2-GP
X1
X-14D31818M-30GP
16
25
11,19
SMBC_ICH
SMBCLK
PCI_SRC_STOP#
PM_STPPCI#
17
17
37
ITP_EN
2
1
11,19
SMBD_ICH
SMBDAT
ITP_EN/PCICLK_F0
CLK_ICHPCI
17
33R2J-2-GP
33R2J-2-GP
R151
R151
1
2
C313
C313
SC39P50V2JN-1GP
SC39P50V2JN-1GP
2
2
ICS954305EKLF-GP
ICS954305EKLF-GP
CLK_MCH_BCLK_1
CLK_CPU_BCLK_1
GEN_REF
2
1
CLK_ICH14
17
CLK_MCH_BCLK_1#
33R2J-2-GP
33R2J-2-GP
R436
R436
CLK_CPU_BCLK_1#
GEN_IREF
2
1
475R2F-L1-GP
475R2F-L1-GP
R438
R438
CLK_XDP_1
2
3
4
CLK_XDP
2
1D05V_S0
CLK_XDP_1#
1
CLK_XDP#
2
RN24
RN24
SRN33J-5-GP-U
SRN33J-5-GP-U
DY
DY
1022
PEG_REFCLKP
PEG_REFCLKN
1
2
4
3
R425
1KR2J-1-GP
DY
RN65
RN65
SRN49D9F-GP
SRN49D9F-GP
R422
R422
R154
R154
CLK_PCIE_NEW
CLK_PCIE_NEW#
2
3
4
CLK_CPU_BCLK
1
2
4
1
CLK_CPU_BCLK#
3
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
RN46
RN46
SRN49D9F-GP
SRN49D9F-GP
RN26
RN26
SRN49D9F-GP
SRN49D9F-GP
CPU_SEL0
4,7
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_MCH_BCLK
2
3
4
1
2
4
CLK_MCH_BCLK#
1
3
CPU_SEL1
4,7
RN54
RN54
SRN49D9F-GP
SRN49D9F-GP
RN47
RN47
SRN49D9F-GP
SRN49D9F-GP
CPU_SEL2
4,7
CLK_PCIE_SATA
CLK_PCIE_SATA#
2
3
4
1
1
1
R427
DUMMY-R2
R424
1KR2J-1-GP
DY
R155
1KR2J-1-GP
DY
FS_C
FS_B
0
FS_A
CPU
RN51
RN51
SRN49D9F-GP
SRN49D9F-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
0
0
266M
CLK_PCIE_ICH
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
2
3
4
2
3
4
0
0
1
133M
CLK_PCIE_ICH#
1
1
0
1
0
200M
RN52
RN52
SRN49D9F-GP
SRN49D9F-GP
RN50
RN50
SRN49D9F-GP
SRN49D9F-GP
0
1
1
166M
1
0
0
333M
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
1
2
4
Title
Title
Title
1
0
1
1
100M
CLK_XDP
CLK_XDP#
3
2
3
4
Clock Generator (IDTCV125PA)
Clock Generator (IDTCV125PA)
Clock Generator (IDTCV125PA)
RN55
RN55
SRN49D9F-GP
SRN49D9F-GP
1
1
0
400M
1
RN48
RN48
SRN49D9F-GP
SRN49D9F-GP
1
1
Reserved
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
DY
DY
KAI
KAI
KAI
SA
SA
SA
A3
A3
A3
Date:
Date:
Date:
Monday, November 28, 2005
Monday, November 28, 2005
Monday, November 28, 2005
Sheet
Sheet
Sheet
3
3
3
of
of
of
44
44
44
A
B
C
D
E
A
B
C
D
E
TP10TPAD30
TP10TPAD30
1
U56A
U56A
1D05V_S0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
J4
H1
6
H_A#[31..3]
A[3]#
ADS#
H_ADS#
6
L4
E2
4
4
A[4]#
BNR#
H_BNR#
6
M3
G5
A[5]#
BPRI#
H_BPRI#
6
K5
A[6]#
M1
H5
R122
56R2J-4-GP
H_DEFER#
6
A[7]#
DEFER#
N2
F21
H_DRDY#
6
A[8]#
DRDY#
J1
E1
H_DBSY#
6
A[9]#
DBSY#
N3
H_DINV#[3..0]
6
A[10]#
Place testpoint on
P5
F1
H_BREQ#0
6
H_DSTBN#[3..0]
6
A[11]#
BR0#
H_IERR# with a GND
0.1" away
P2
H_DSTBP#[3..0]
6
A[12]#
H_IERR#
L1
D20
A[13]#
IERR#
P4
B3
H_INIT#
16
A[14]#
INIT#
P1
A[15]#
R1
H4
H_LOCK#
6
H_D#[63..0]
6
A[16]#
LOCK#
U56B
U56B
L2
H_CPURST#
2,6
H_RS#[2..0]
6
H_ADSTB#0
ADSTB[0]#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#41
B1
E22
AA23
6
6
H_REQ#[4..0]
RESET#
D[0]#
D[32]#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#2
K3
F3
F24
AB24
REQ[0]#
RS[0]#
D[1]#
D[33]#
H_RS#1
H2
F4
E26
V24
REQ[1]#
RS[1]#
D[2]#
D[34]#
K2
G3
H22
V26
REQ[2]#
RS[2]#
D[3]#
D[35]#
J3
G2
F23
W25
H_TRDY#
6
REQ[3]#
TRDY#
D[4]#
D[36]#
L5
G25
U23
REQ[4]#
D[5]#
D[37]#
G6
E25
U25
H_HIT#
6
HIT#
D[6]#
D[38]#
H_A#17
H_A#19
Y2
E4
E23
U22
H_HITM#
6
A[17]#
HITM#
D[7]#
D[39]#
H_A#18
H_A#20
H_A#21
H_A#22
H_D#40
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
U5
K24
AB25
A[18]#
D[8]#
D[40]#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
R3
AD4
G24
W22
XDP_BPM#0 2
XDP_BPM#1 2
XDP_BPM#2 2
XDP_BPM#3 2
XDP_BPM#4 2
XDP_BPM#5 2
XDP_TCK 2
XDP_TDI 2
XDP_TMS 2
XDP_TRST# 2
A[19]#
BPM[0]#
D[9]#
D[41]#
W6
AD3
J24
Y23
A[20]#
BPM[1]#
D[10]#
D[42]#
U4
AD1
J23
AA26
A[21]#
BPM[2]#
D[11]#
D[43]#
Y5
AC4
H26
Y26
A[22]#
BPM[3]#
D[12]#
D[44]#
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
U2
AC2
F26
Y22
A[23]#
PRDY#
D[13]#
D[45]#
1D05V_S0
R4
AC1
XDP_BPM#5
K22
AC26
A[24]#
PREQ#
D[14]#
D[46]#
3
3
T5
AC5
H25
AA24
A[25]#
TCK
D[15]#
D[47]#
T3
AA6
H23
W24
6
H_DSTBN#0
H_DSTBN#2
6
A[26]#
TDI
DSTBN[0]#
DSTBN[2]#
XDP_TDO
R123
68R2-GP
W3
AB3
G22
Y25
XDP_TDO
2
6
H_DSTBP#0
H_DSTBP#2
6
A[27]#
TDO
DSTBP[0]#
DSTBP[2]#
W5
AB5
J26
V23
6
H_DINV#0
H_DINV#2
6
A[28]#
TMS
DINV[0]#
DINV[2]#
Y4
AB6
A[29]#
TRST#
XDP_DBRESET#
W2
C20
XDP_DBRESET#
2,17
A[30]#
DBR#
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#48
H_D#49
H_D#51
Y1
N22
AC22
A[31]#
D[16]#
D[48]#
CPU_PROCHOT#_1
V4
D21
1
2
K25
AC23
6
H_ADSTB#1
CPU_PROCHOT#
34
ADSTB[1]#
PROCHOT#
D[17]#
D[49]#
R127
R127
DY
DY
0R2J-2-GP
0R2J-2-GP
H_D#50
H_D#52
H_D#53
H_D#54
H_D#55
H_D#57
A24
P26
AB22
H_THERMDA
20
THERMDA
D[18]#
D[50]#
A6
A25
R23
AA21
16
H_A20M#
H_THERMDC 20
PM_THRMTRIP-A#
A20M#
THERMDC
D[19]#
D[51]#
A5
L25
AB21
16
H_FERR#
7
FERR#
D[20]#
D[52]#
C4
C7
L22
AC25
16
H_IGNNE#
IGNNE#
THERMTRIP#
D[21]#
D[53]#
1
2
L23
AD20
PM_THRMTRIP-I#
16
D[22]#
D[54]#
R109
R109
0R2J-2-GP
0R2J-2-GP
D5
M23
AE22
16
H_STPCLK#
STPCLK#
D[23]#
D[55]#
H_D#56
H_D#58
H_D#59
H_D#60
H_D#61
H_D#63
C6
P25
AF23
16
H_INTR
LINT0
D[24]#
D[56]#
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
Comp1, 3 connect with Zo=55 ohm, make
B4
A22
P22
AD24
16
H_NMI
CLK_CPU_BCLK
3
LINT1
BCLK[0]
D[25]#
D[57]#
A3
A21
P23
AE21
16
H_SMI#
CLK_CPU_BCLK#
3
SMI#
BCLK[1]
D[26]#
D[58]#
T24
AD21
trace length shorter than 0.5" .
trace length shorter than 0.5" .
D[27]#
D[59]#
TPAD30
TPAD30
TP15
TP15
1
AA1
R24
AE25
RSVD[01]
D[28]#
D[60]#
TPAD30
TPAD30
TP18
TP18
TP24
TP24
TPAD30
TPAD30
1
AA4
T22
1
L26
AF25
RSVD[02]
RSVD[12]
D[29]#
D[61]#
1D05V_S0
TPAD30
TPAD30
TP16
TP16
H_D#62
1
AB2
T25
AF22
RSVD[03]
D[30]#
D[62]#
TPAD30
TPAD30
TP17
TP17
1
AA3
N24
AF26
RSVD[04]
D[31]#
D[63]#
TPAD30
TPAD30
TP11
TP11
1
M4
D2
1
TP7
TP7
TPAD30
TPAD30
M24
AD23
RSVD[05]
RSVD[13]
6
H_DSTBN#1
DSTBN[1]#
DSTBN[3]#
H_DSTBN#3
6
TPAD30
TPAD30
TP12
TP12
1
N5
F6
1
TP9
TP9
TPAD30
TPAD30
R131
1KR2F-3-GP
N25
AE24
6
H_DSTBP#1
H_DSTBP#3
6
RSVD[06]
RSVD[14]
DSTBP[1]#
DSTBP[3]#
TPAD30
TPAD30
TP13
TP13
1
T2
D3
1
TP8
TP8
TPAD30
TPAD30
M26
AC20
6
H_DINV#1
H_DINV#3
6
RSVD[07]
RSVD[15]
DINV[1]#
DINV[3]#
TPAD30
TPAD30
TP14
TP14
TP6
TP6
TPAD30
TPAD30
1
V3
C1
1
RSVD[08]
RSVD[16]
TPAD30
TPAD30
TP4
TP4
TP19
TP19
TPAD30
TPAD30
Layout Note:
0.5" max length.
CPU_GTLREF0
COMP0
COMP1
COMP2
COMP3
1
B2
AF1
1
AD26
R26
1
2
RSVD[09]
RSVD[17]
GTLREF
COMP[0]
TPAD30
TPAD30
TP5
TP5
TP23
TP23
TPAD30
TPAD30
MISC
MISC
R128
R128
27D4R2F-L1-GP
27D4R2F-L1-GP
1
C3
D22
1
U26
1
2
RSVD[10]
RSVD[18]
COMP[1]
TP22
TP22
TPAD30
TPAD30
R129
R129
54D9R2F-L1-GP
54D9R2F-L1-GP
C23
1
U1
1
2
RSVD[19]
COMP[2]
2
2
TPAD30
TPAD30
TP20
TP20
TP21
TP21
TPAD30
TPAD30
R130
2KR2F-3-GP
TEST1
TEST2
R112
R112
27D4R2F-L1-GP
27D4R2F-L1-GP
1
B25
C24
1
2
R406
1
C26
V1
1
2
RSVD[11]
RSVD[20]
TEST1
COMP[3]
R406
DY
DY
1KR2J-1-GP
1KR2J-1-GP
R113
R113
54D9R2F-L1-GP
54D9R2F-L1-GP
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
1
2
D25
E5
H_DPRSTP# 16
H_DPSLP# 16
H_DPWR# 6
H_PWRGD 16
H_CPUSLP#
TEST2
DPRSTP#
R407
R407
51R2J-2-GP
51R2J-2-GP
B5
DPSLP#
D24
DPWR#
B22
D6
3,7
CPU_SEL0
BSEL[0]
PWRGOOD
B23
D7
3,7
CPU_SEL1
6,16
BSEL[1]
SLP#
C21
AE6
3,7
CPU_SEL2
PSI#
34
BSEL[2]
PSI#
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
1D05V_S0
1D05V_S0
R120
R120
XDP_TDI
1
2
H_PWRGD
1
2
150R2J-L1-GP-U
150R2J-L1-GP-U
R111
R111
200R2J-L1-GP
200R2J-L1-GP
<Core Design>
<Core Design>
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
KAI
KAI
KAI
SA
SA
SA
Date:
Date:
Date:
Monday, November 28, 2005
Monday, November 28, 2005
Monday, November 28, 2005
Sheet
Sheet
Sheet
4
4
4
of
of
of
44
44
44
A
B
C
D
E
A
B
C
D
E
VCC_CORE_S0
U56D
U56D
A4
P6
VSS[001]
VSS[082]
VCC_CORE_S0
A8
P21
VSS[002]
VSS[083]
A11
P24
VSS[003]
VSS[084]
A14
R2
VSS[004]
VSS[085]
U56C
U56C
A16
R5
VSS[005]
VSS[086]
A7
AB20
A19
R22
VCC[001]
VCC[068]
VSS[006]
VSS[087]
A9
AB7
A23
R25
VCC[002]
VCC[069]
VSS[007]
VSS[088]
A10
AC7
A26
T1
VCC[003]
VCC[070]
VSS[008]
VSS[089]
A12
AC9
B6
T4
VCC[004]
VCC[071]
VSS[009]
VSS[090]
A13
AC12
B8
T23
VCC[005]
VCC[072]
VSS[010]
VSS[091]
A15
AC13
B11
T26
VCC[006]
VCC[073]
VSS[011]
VSS[092]
A17
AC15
B13
U3
VCC[007]
VCC[074]
VSS[012]
VSS[093]
A18
AC17
B16
U6
4
4
VCC[008]
VCC[075]
VSS[013]
VSS[094]
A20
AC18
B19
U21
VCC[009]
VCC[076]
VSS[014]
VSS[095]
B7
AD7
B21
U24
VCC[010]
VCC[077]
VSS[015]
VSS[096]
B9
AD9
B24
V2
VCC[011]
VCC[078]
VSS[016]
VSS[097]
B10
AD10
C5
V5
VCC[012]
VCC[079]
VSS[017]
VSS[098]
B12
AD12
C8
V22
VCC[013]
VCC[080]
VSS[018]
VSS[099]
B14
AD14
C11
V25
VCC[014]
VCC[081]
VSS[019]
VSS[100]
B15
AD15
C14
W1
VCC[015]
VCC[082]
VSS[020]
VSS[101]
B17
AD17
C16
W4
VCC[016]
VCC[083]
VSS[021]
VSS[102]
B18
AD18
C19
W23
VCC[017]
VCC[084]
VSS[022]
VSS[103]
B20
AE9
C2
W26
VCC[018]
VCC[085]
VSS[023]
VSS[104]
C9
AE10
C22
Y3
VCC[019]
VCC[086]
VSS[024]
VSS[105]
C10
AE12
C25
Y6
VCC[020]
VCC[087]
VSS[025]
VSS[106]
C12
AE13
D1
Y21
VCC[021]
VCC[088]
VSS[026]
VSS[107]
C13
AE15
D4
Y24
VCC[022]
VCC[089]
VSS[027]
VSS[108]
C15
AE17
D8
AA2
VCC[023]
VCC[090]
VSS[028]
VSS[109]
C17
AE18
D11
AA5
VCC[024]
VCC[091]
VSS[029]
VSS[110]
C18
AE20
D13
AA8
VCC[025]
VCC[092]
VSS[030]
VSS[111]
D9
AF9
D16
AA11
VCC[026]
VCC[093]
VSS[031]
VSS[112]
D10
AF10
D19
AA14
VCC[027]
VCC[094]
VSS[032]
VSS[113]
D12
AF12
D23
AA16
VCC[028]
VCC[095]
VSS[033]
VSS[114]
D14
AF14
D26
AA19
VCC[029]
VCC[096]
VSS[034]
VSS[115]
D15
AF15
E3
AA22
VCC[030]
VCC[097]
VSS[035]
VSS[116]
D17
AF17
E6
AA25
VCC[031]
VCC[098]
VSS[036]
VSS[117]
D18
AF18
E8
AB1
VCC[032]
VCC[099]
VSS[037]
VSS[118]
1D05V_S0
E7
AF20
E11
AB4
VCC[033]
VCC[100]
VSS[038]
VSS[119]
E9
E14
AB8
VCC[034]
VSS[039]
VSS[120]
E10
V6
E16
AB11
VCC[035]
VCCP[01]
VSS[040]
VSS[121]
E12
G21
E19
AB13
VCC[036]
VCCP[02]
VSS[041]
VSS[122]
3
3
E13
J6
E21
AB16
VCC[037]
VCCP[03]
VSS[042]
VSS[123]
E15
K6
E24
AB19
VCC[038]
VCCP[04]
VSS[043]
VSS[124]
E17
M6
F5
AB23
VCC[039]
VCCP[05]
VSS[044]
VSS[125]
E18
J21
F8
AB26
VCC[040]
VCCP[06]
VSS[045]
VSS[126]
E20
K21
F11
AC3
VCC[041]
VCCP[07]
VSS[046]
VSS[127]
F7
M21
F13
AC6
34
H_VID[0..6]
VCC[042]
VCCP[08]
VSS[047]
VSS[128]
1D5V_S0
1D5V_VCCA_S0
F9
N21
F16
AC8
VCC[043]
VCCP[09]
VSS[048]
VSS[129]
F10
N6
F19
AC11
VCC[044]
VCCP[10]
VSS[049]
VSS[130]
F12
R21
F2
AC14
VCC[045]
VCCP[11]
VSS[050]
VSS[131]
F14
R6
1
2
F22
AC16
VCC[046]
VCCP[12]
VSS[051]
VSS[132]
R126
R126
0R0603-PAD
0R0603-PAD
F15
T21
F25
AC19
VCC[047]
VCCP[13]
VSS[052]
VSS[133]
F17
T6
G4
AC21
VCC[048]
VCCP[14]
VSS[053]
VSS[134]
1D5V_VCCA_S0
F18
V21
G1
AC24
VCC[049]
VCCP[15]
VSS[054]
VSS[135]
F20
W21
G23
AD2
VCC[050]
VCCP[16]
VSS[055]
VSS[136]
AA7
G26
AD5
VCC[051]
VSS[056]
VSS[137]
AA9
B26
H3
AD8
VCC[052]
VCCA
VSS[057]
VSS[138]
AA10
H6
AD11
VCC[053]
VSS[058]
VSS[139]
AA12
H21
AD13
VCC[054]
VSS[059]
VSS[140]
1D05V_S0
C291
SCD01U16V2KX-3GP
C290
SC10U10V5ZY-1GP
AA13
AD6
H24
AD16
H_VID0
34
VCC[055]
VID[0]
VSS[060]
VSS[141]
AA15
AF5
J2
AD19
H_VID1
34
VCC[056]
VID[1]
VSS[061]
VSS[142]
VCC_CORE_S0
AA17
AE5
J5
AD22
VCC[057]
VID[2]
H_VID2
34
VSS[062]
VSS[143]
AA18
AF4
J22
AD25
VCC[058]
VID[3]
H_VID3
34
VSS[063]
VSS[144]
AA20
AE3
J25
AE1
VCC[059]
VID[4]
H_VID4
34
VSS[064]
VSS[145]
AB9
AF2
K1
AE4
H_VID5
34
VCC[060]
VID[5]
VSS[065]
VSS[146]
AC10
AE2
R121
100R2F-L1-GP-U
C271
C264
C274
C239
C270
C269
C238
C240
C237
C234
K4
AE8
H_VID6
34
VCC[061]
VID[6]
VSS[066]
VSS[147]
TC4
ST220U2D5VBM-LGP
DY
AB10
K23
AE11
VCC[062]
VSS[067]
VSS[148]
AB12
K26
AE14
VCC[063]
VSS[068]
VSS[149]
AB14
AF7
L3
AE16
VCC_SENSE
34
VCC[064]
VCCSENSE
VSS[069]
VSS[150]
AB15
L6
AE19
VCC[065]
VSS[070]
VSS[151]
2
2
AB17
L21
AE23
VCC[066]
VSS[071]
VSS[152]
AB18
AE7
L24
AE26
VSS_SENSE
34
VCC[067]
VSSSENSE
VSS[072]
VSS[153]
M2
AF3
VSS[073]
VSS[154]
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
M5
AF6
VSS[074]
VSS[155]
R114
100R2F-L1-GP-U
M22
AF8
VSS[075]
VSS[156]
VCC_CORE_S0
M25
AF11
VSS[076]
VSS[157]
N1
AF13
VSS[077]
VSS[158]
N4
AF16
VSS[078]
VSS[159]
N23
AF19
VSS[079]
VSS[160]
C236
C232
C235
C233
C268
C266
C267
C265
C229
C231
C230
C275
C272
C276
C273
C244
C242
C243
N26
AF21
VSS[080]
VSS[161]
P3
AF24
VSS[081]
VSS[162]
BGA479-SKT6-GPU1
BGA479-SKT6-GPU1
VCC_CORE_S0
VCC_CORE_S0
Layout Note:
VCCSENSE and VSSSENSE lines
should be of equal length.
C241
C263
C262
C228
C247
C246
C248
C245
C279
C277
C278
C261
<Core Design>
<Core Design>
<Core Design>
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
KAI
KAI
KAI
SA
SA
SA
Date:
Date:
Date:
Monday, November 28, 2005
Monday, November 28, 2005
Monday, November 28, 2005
Sheet
Sheet
Sheet
5
5
5
of
of
of
44
44
44
A
B
C
D
E
Plik z chomika:
joseeph
Inne pliki z tego folderu:
Wistron D-Note_IBM X30.pdf
(1206 KB)
Wistron jm41_jm51_-2_final.pdf
(502 KB)
Wistron (D)H2 rev.-4.pdf
(1320 KB)
Wistron (UNKNOWN).pdf
(1672 KB)
Wistron 1846.pdf
(1037 KB)
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