OP282_48.PDF

Dual/Quad Low Power, High Speed

JFET Operational Amplifiers

OP282/OP482

FEATURES

High Slew Rate: 9 V/ m s

Wide Bandwidth: 4 MHz

Low Supply Current: 250 m A/Amplifier

Low Offset Voltage: 3 mV

Low Bias Current: 100 pA

Fast Settling Time

Common-Mode Range Includes V+

Unity Gain Stable

PIN CONNECTIONS

8-Lead Narrow-Body SOIC

8-Lead Epoxy DIP

(S Suffix)

(P Suffix)

OUT A

–IN A

+IN A

V–

V+

OUT A

–IN A

+IN A

V–

V+

OP282

OUT B

–IN B

OUT B

–IN B

OP282

+IN B

OP-482

+IN B

APPLICATIONS

Active Filters

Fast Amplifiers

Integrators

Supply Current Monitoring

14-Lead Epoxy DIP

14-Lead Narrow-Body SOIC

(P Suffix)

(S Suffix)

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

OUT D

–IN D

+IN D

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

GENERAL DESCRIPTION

The OP282/OP482 dual and quad operational amplifiers feature

excellent speed at exceptionally low supply currents. Slew rate

exceeds 7 V/ms with supply current under 250 mA per amplifier.

These unity gain stable amplifiers have a typical gain bandwidth

of 4 MHz.

The JFET input stage of the OP282/OP482 insures bias current

is typically a few picoamps and below 500 pA over the full

temperature range. Offset voltage is under 3 mV for the dual

and under 4 mV for the quad.

With a wide output swing, within 1.5 volts of each supply, low

power consumption and high slew rate, the OP282/OP482 are

ideal for battery-powered systems or power restricted applica-

tions. An input common-mode range that includes the positive

supply makes the OP282/OP482 an excellent choice for high-

side signal conditioning.

The OP282/OP482 are specified over the extended industrial

temperature range. Both dual and quad amplifiers are available

in plastic and ceramic DIP plus SOIC surface mount packages.

–IN D

+IN D

OP482

V–

+IN C

–IN C

OUT C

OP482

V–

+IN C

–IN C

OUT C

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

OP282/OP482–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS (@ V S = 6 15.0 V, T A = +25 8 C unless otherwise noted)

Parameter

Symbol

Conditions

Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage

V OS

OP282

0.2

OP282, –40 £ T A £ +85°C

4.5

Offset Voltage

V OS

OP482

0.2

OP482, –40 £ T A £ +85°C

Input Bias Current

I B

V CM = 0 V

100

V CM = 0 V, Note 1

500

Input Offset Current

I OS

V CM = 0 V

V CM = 0 V, Note 1

250

Input Voltage Range

–11

+15

Common-Mode Rejection

CMR

–11 V £ V CM £ +15 V, –40 £ T A £ +85°C70

Large Signal Voltage Gain

A VO

R L = 10 kW

V/mV

R L = 10 kW, –40 £ T A £ +85°C

V/mV

Offset Voltage Drift

DV OS /DT

mV/°C

Bias Current Drift

DI B /DT

pA/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing

V O

R L = 10 kW

–13.5

± 13.9 13.5 V

Short Circuit Limit

I SC

Source

Sink

–8

–12

Open-Loop Output Impedance

Z OUT

f = 1 MHz

200

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

V S = ± 4.5 V to ± 18 V,

–40 £ T A £ +85°C

316

mV/V

Supply Current/Amplifier

I SY

V O = 0 V, 40 £ T A £ +85°C

210

250

Supply Voltage Range

V S

± 4.5

± 18

DYNAMIC PERFORMANCE

Slew Rate

R L = 10 kW

V/ms

Full-Power Bandwidth

BW P

1% Distortion

125

kHz

Settling Time

t S

To 0.01%

1.6

Gain Bandwidth Product

GBP

MHz

Phase Margin

Ø O

Degrees

NOISE PERFORMANCE

Voltage Noise

e n p-p

0.1 Hz to 10 Hz

1.3

mV p-p

Voltage Noise Density

e n

f = 1 kHz

nV/ÖHz

Current Noise Density

i n

0.01

pA/ÖHz

NOTE

1 The input bias and offset currents are tested at T A = T J = +85

C. Bias and offset currents are guaranteed but not tested at –40

Specifications subject to change without notice.

WAFER TEST LIMITS (@ V S = 6 15.0 V, T A = +25 8 C unless otherwise noted)

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

V OS

OP282

mV max

Offset Voltage

V OS

OP482

mV max

Input Bias Current

I B

V CM = 0 V

100

pA max

Input Offset Current

I OS

V CM = 0 V

pA max

Input Voltage Range 1

–11, +15

V min/max

Common-Mode Rejection

CMRR

–11 V £ V CM £ +15 V

dB min

Power Supply Rejection Ratio

PSRR

V = ± 4.5 V to ± 18 V

316

mV/V

Large Signal Voltage Gain

A VO

R L = 10 kW

V/mV min

Output Voltage Range

V O

R L = 10 kW

± 13.5

V min

Supply Current/Amplifier

I SY

V O = 0 V, R L = ¥

250

mA max

NOTES

Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

1 Guaranteed by CMR test.

Specifications subject to change without notice.

–2–

REV. B

OP282/OP482

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Differential Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . 36 V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C

OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C

DICE CHARACTERISTICS

Package Type

u JA 2

u JC

Units

8-Pin Plastic DIP (P)

103

°C/W

OP282 Die Size 0.063 3 0.060 Inch, 3,780 Sq. Mils

8-Pin SOIC (S)

158

°C/W

14-Pin Plastic DIP (P)

°C/W

14-Pin SOIC (S)

120

°C/W

NOTES

1 For supply voltages less than

18 V, the absolute maximum input voltage is

equal to the supply voltage.

q JA is specified for the worst case conditions, i.e.,

q JA is specified for device soldered in circuit board for

q JA is specified for device in

SOIC package.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

OP282GP

–40°C to +85°C 8-Pin Plastic DIP N-8

OP282GS

–40°C to +85°C 8-Pin SOIC

SO-8

OP482GP

–40°C to +85°C 14-Pin Plastic DIP N-14

OP482GS

–40°C to +85°C 14-Pin SOIC

SO-14

OP482 Die Size 0.070 3 0.098 Inch, 6,860 Sq. Mils

REV. B

–3–

socket for cerdip, P-DIP;

OP282/OP482

APPLICATIONS INFORMATION

The OP282 and OP482 are single and dual JFET op amps that

have been optimized for high speed at low power. This

combination makes these amplifiers excellent choices for battery

powered or low power applications requiring above average

performance. Applications benefiting from this performance

combination include telecom, geophysical exploration, portable

medical equipment and navigational instrumentation.

PHASE INVERSION

Most JFET-input amplifiers will invert the phase of the input

signal if either input exceeds the input common-mode range.

For the OP282 and OP482 negative signals in excess of approxi-

mately 14 volts will cause phase inversion. The cause of this

effect is saturation of the input stage leading to the forward-

biasing of a drain-gate diode. A simple fix for this in noninverting

applications is to place a resistor in series with the noninverting

input. This limits the amount of current through the forward-

biased diode and prevents the shutting down of the output

stage. For the OP282/OP482, a value of 200 kW has been found

to work. However, this adds a significant amount of noise.

HIGH SIDE SIGNAL CONDITIONING

There are many applications that require the sensing of signals

near the positive rail. OP282s and OP482s have been tested and

guaranteed over a common-mode range (–11 V £ V CM £ +15 V)

that includes the positive supply.

One application where this is commonly used is in the sensing of

power supply currents. This enables it to be used in current

sensing applications such as the partial circuit shown in Figure

1. In this circuit, the voltage drop across a low value resistor,

such as the 0.1 W shown here, is amplified and compared to 7.5

volts. The output can then be used for current limiting.

+15V

0.1

-5

500k

100k

-10

R L

100k

-15

-10

-5

OUT

1/2

OP282

Figure 2. OP282 Phase Reversal

100k

Figure 1. Phase Inversion

ACTIVE FILTERS

The OP282 and OP482’s wide bandwidth and high slew rates

make either an excellent choice for many filter applications.

There are many types of active filter configurations, but the four

most popular configurations are Butterworth, elliptical, Bessel,

and Chebyshev. Each type has a response that is optimized for a

given characteristic as shown in Table I.

PROGRAMMABLE STATE-VARIABLE FILTER

Table I.

Amplitude

Type

Selectivity Overshoot

Phase

(Pass Band)

(Stop Band)

Butterworth

Moderate

Good

Max Flat

Chebyshev

Good

Moderate

Nonlinear Equal Ripple

Elliptical

Best

Poor

Equal Ripple

Bessel (Thompson)

Poor

Best

Linear

–4–

REV. B

OP282/OP482

The circuit shown in Figure 3 can be used to accurately

program the “Q,” the cutoff frequency f C , and the gain of a two

pole state-variable filter. OP482s have been used in this design

because of their high bandwidths, low power and low noise.

This circuit takes only three packages to build because of the

quad configuration of the op amps and DACs.

The DACs shown are all used in the voltage mode so all values

are dependent only on the accuracy of the DAC and not on the

absolute values of the DAC’s resistive ladders. This make this

circuit unusually accurate for a programmable filter.

Adjusting DAC 1 changes the signal amplitude across R1;

therefore, the DAC attenuation times R1 determines the

amount of signal current that charges the integrating capacitor,

C1. This cutoff frequency can now be expressed as:

fc =

2p R 1 C 1

D 1

256

where D 1 is the digital code for the DAC.

Gain of this circuit is set by adjusting D 3 . The gain equation is:

Gain

R 4

R 5

D 3

256

DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC

controls the amount of feedback from the bandpass node to the

input summing node. Note that the digital value of the DAC is

in the numerator, therefore zero code is not a valid operating point.

Q =

R 2

R 3

256

D 2

1/4

DAC8408

1/4

DAC8408

1000pF

1/4

DAC8408

1000pF

V IN

1/4

OP482

1/4

OP482

1/4

OP482

1/4

OP482

1/4

OP482

LOW

PASS

1/4

OP482

HIGH PASS

1/4

DAC8408

BANDPASS

1/4

OP482

1/4

OP482

Figure 3.

REV. B

–5–

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