l3_combi_veri(1).pdf

L3: Introduction to Verilog

Verilog

(Combinational Logic)

Acknowledgements :

Materials in this lecture are courtesy of the following sources and are used with

permission.

Rex Min

Verilog References:

• Samir Palnitkar, Verilog HDL , Pearson Education (2nd edition).

• Donald Thomas, Philip Moorby, The Verilog Hardware Description Language , Fifth

Edition, Kluwer Academic Publishers.

• J. Bhasker, Verilog HDL Synthesis (A Practical Primer) , Star Galaxy Publishing

L3: 6.111 Spring 2006

Introductory Digital Systems Laboratory

L3: Introduction to

(Combinational Logic)

Synthesis and HDLs

HDLs

Hardware description language (HDL) is a convenient, device-

independent representation of digital logic

Verilog

input a,b;

output sum;

assign sum <= {1b’0, a} + {1b’0, b};

Compilation and

Synthesis

HDL description is compiled

into a netlist

Netlist

Synthesis optimizes the logic

g1 "and" n1 n2 n5

g2 "and" n3 n4 n6

g3 "or" n5 n6 n7

Mapping targets a specific

hardware platform

Mapping

FPGA

PAL

ASIC

(Custom ICs)

L3: 6.111 Spring 200

Introductory Digital Systems Laboratory

Synthesis and

The FPGA: A Conceptual View

An FPGA is like an electronic breadboard that is wired together

by an automated synthesis tool

Built-in components are called macros

SUM

sel

interconnect

counter

LUT

F(a,b,c,d)

G(a,b,c,d)

ADR

RAM

DATA

R/W

(for everything else)

L3: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Synthesis and Mapping for FPGAs

FPGAs

Infer macros: choose the FPGA macros that efficiently

implement various parts of the HDL code

...

always @ (posedge clk)

begin

count <= count + 1;

“This section of code looks

like a counter. My FPGA has

some of those...”

counter

end

...

HDL Code

Inferred Macro

Place-and-route: with area and/or speed in mind, choose

the needed macros by location and route the interconnect

“This design only uses 10% of

the FPGA. Let’s use the macros

in one corner to minimize the

distance between blocks.”

L3: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Synthesis and Mapping for

Verilog : The Module

: The Module

Verilog designs consist of

interconnected modules .

out

A module can be an element or

collection of lower level design blocks.

outbar

A simple module with combinational

logic might look like this:

sel

Out = sel ● a + sel ● b

2-to-1 multiplexer with inverted output

module mux_2_to_1(a, b, out,

Declare and name a module; list its

ports. Don’t forget that semicolon.

outbar, sel);

// This is 2:1 multiplexor

Comment starts with //

Verilog skips from // to end of the line

input a, b, sel;

Specify each port as input, output,

or inout

output out, outbar;

assign out = sel ? a : b;

Express the module’s behavior.

Each statement executes in

parallel; order does not matter.

assign outbar = ~out;

endmodule

Conclude the module code.

L3: 6.111 Spring 2006

Introductory Digital Systems Laboratory

Verilog

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