KS32C5000.PDF

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Microsoft PowerPoint - P32C50~3
KS32C5000
Main Features of Product(KS32C5000)
LSI
Division
„ 32-bit S-ARM7T RISC Core
„ 8 Kbytes Unified Cache / SRAM(8K Cache, 4K/4K
Cache/SRAM, or 8K SRAM Mode)
„ 2-channel UART
„ 2-channel HDLC with DMA
„ IIC Bus (Simple master)
„ 2-channel DMA
„ 2-channel 32-bit Timers
„ 10/100Mbps Ethernet Controller(MAC)
„ Interrupt controller
„ Fast Page/EDO Mode DRAM Controller with CBR
Refresh and Self Refresh Control
„ SRAM/ROM Controller
„ Interrupt controller
„ 208 QFP
„ M/P : ‘98. 5(E/S : Available)
S-ARM7T
(33MHz)
MAC
(10/100M)
2-ch HDLC
(with DMA)
I&D
Cache
2-ch UART
SRAM
2-ch Timer
Memory
Controller
IIC Bus
Interrupt
Controller
2-ch DMA
May ‘98
3
ELECTRONICS
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KS32C5000
Main Features of Product(KS32C5100)
LSI
Division
„ 32-bit S-ARM7T RISC Core (66MHz@3.3V)
„ 8 Kbytes Unified Cache
„ 4Kbytes SRAM
„ 2-channel UART
„ 4-channel HDLC with dedicated DMA
„ IIC Bus (Simple master)
„ 6-channel DMA
„ 2-channel Timers(32-bit)
„ Watchdog Timer(16-bit)
„ 10/100Mbps Ethernet Controller(MAC)
„ Host-to-PCI bridge unit
„ 4 External bus request
„ Interrupt controller
„ EDO Mode DRAM/ Synchronous DRAM Controller
with CBR Refresh and Self Refresh Control
„ SRAM/ROM/Flash Controller
„ 22 Programmable I/O ports
„ PLL
„ 256 QFP
„ M/P : ‘99. 3(E/S : ‘98. 12)
S-ARM7T
(66MHz)
MAC
(10/100M)
4-ch HDLC
I&D
Cache
(8K)
Host to PCI
Bridge
SRAM
(2K)
2-ch UART
Memory
Controller
(EDO/SDRAM)
2-ch Timer
(32-bit)
IIC Bus
Interrupt
Controller
6-ch DMA
PLL
2-ch UART
May ‘98
4
ELECTRONICS
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KS32C5000
Application Block Diagram (Ethernet Hub/Router)
LSI
Division
Memory
Memory
Remote Port(RS-232/V.35)
CPU Bus
S-ARM7T
HDLC
RIC
Cache(SRAM)
8KB
DMAC x 2
I2C
TIMER
DMAC
INTC
UART
Ethernet
Controller
MAC
10/100Mbps
RIC
BDMA
KS32C5000
Inter-RIC Bus
Filter Module
May ‘98
5
ELECTRONICS
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KS32C5000
Application Block Diagram (Ethernet Switch)
LSI
Division
Memory
Memory
CPU BUS
S-ARM7T
HDLC
Quad
MAC
Quad
PHY
DMAC x 2
Quad
MAC
Quad
PHY
Cache(SRAM)
8KB
Switched
Ethernet
Engine
I2C
TIMER
DMAC
INTC
UART
Ethernet
Controller
Quad
MAC
Quad
PHY
MAC
10/100Mbps
Quad
MAC
Quad
PHY
BDMA
KS32C5000
May ‘98
6
ELECTRONICS
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KS32C5000
Application Block Diagram (Cable Modem)
LSI
Division
Memory
Memory
From Headend
CPU BUS
Receiver
S-ARM7T
HDLC
DMAC x 2
Cable
Tuner
3’rd
Mixer
ADC
QUAM
Demod.
FEC
Cache(SRAM)
8KB
Transmitter
Ethernet
Controller
Wide
Band
Filter
10-bit
DAC
QPSK
/QAM
Mod.
RS
Encode
I2C
TIMER
DMAC
INTC
UART
MAC
10/100Mbps
PC
I/F
BDMA
Ethernet 10/100
ATM25
PCI/USB
etc
To Headend
KS32C5000
May ‘98
7
ELECTRONICS
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