EMIF08-VID01F2.pdf

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EMIF08-VID01F2
8 line low capacitance EMI filter
and ESD protection
Main product characteristics
Where EMI filtering in ESD sensitive equipment is
required :
■
LCD & camera for mobile phones
■
Computers and printers
■
Communication systems
■
MCU Boards
Description
Lead free flip chip package
The EMIF08-VID01F2 is an 8 line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The flip chip packaging means the
package size is equal to the die size.
efrcom
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15kV.
12 11 10
9 8 7
6 5 4
3 2 1
I8
I7
I6
I5
I4
I3
I2
I1
A
Benefits
GND
GND
ic
GND
GND
B
■
High efficiency EMI filter (-33 dB @ 900 Mhz)
O8
O7
O6
O5
O4
O3
O2
O1
C
efrcom
■
Low line capacitance suitable for high speed
data bus
C
■
Low serial resistance for camera impedance
adaptation
O8
O7
O6
O5
O4
O3
O2
O1
GND
GND
board
GND
GND
B
■
Optimized PCB space consuming: 1.29 mm x
3.92 mm
I8
I7
I6
I5
I4
I3
I2
I1
A
■
Very thin package: 0.65 mm
12 11 10
9 8 7
6 5 4
3 2 1
■
Lead free pacakge
Complies with following standards:
■
High efficiency in ESD suppression on inputs
pins (IEC61000-4-2 level 4).
IEC61000-4-2
■
High reliability offered by monolithic integration
level 4 input pins
15 kV (air discharge)
8 kV
(contact discharge
High reducing of parasitic elements through
integration & wafer level packaging.
■
level 1 output pins 2 kV
(air discharge)
2 kV
(contact discharge
MIL STD 883E - Method 3015-6 Class 3
Rev 2
August 2005
1/6
www.st.com
6
Pin configuration (Bumps side)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
356213252.011.png
1 Electrical characteristics (T amb = 25°C)
EMIF08-VID01F2
Figure 1. Basic cell configuration
Input
Output
R
R = 100
C line = 16 pF typ. @ 3 V
Ω
Table 1.
Absolute ratings (limiting values)
Symbol
Parameter
Value
Unit
Vpp
ESD discharge IEC61000-4-2 air discharge
ESD discharge IEC61000-4-2 contact discharge
15
8
kV
KV
Tj
Maximum junction temperature
125
°C
T op
Operating temperature range
-40 to +85
°C
T stg
Storage temperature range
-55 to +150
°C
1
Electrical characteristics (T amb = 25°C)
Symbol
Parameters
I
V BR
Breakdown voltage
I RM
Leakage current @ V RM
V RM
Stand-off voltage
I RM
V
V RM V BR
R
Series resistance between Input &
Output
C line
Input capacitance per line
Symbol
Test conditions
Min
Typ
Max
Unit
V BR
I R = 1mA
6
8
10
V
I RM
V RM = 3V per line
500
nA
R I/O
I=10mA
80
100
120
Ω
C line
V R = 3V DC, 1 MHz
16
19
pF
2/6
I
I RM
V
V RM V BR
356213252.012.png 356213252.013.png 356213252.014.png
EMIF08-VID01F2
1 Electrical characteristics (T amb = 25°C)
Figure 2. S21 (dB) attenuation measurement Figure 3. Analog crosstalk measurement
dB
dB
0
0
-10
-5
-20
-10
-30
-15
-40
-20
-50
-25
-60
-30
-70
-35
-80
-40
-90
f (Hz)
f (Hz)
-100
-45
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Figure 4. ESD response to IEC61000-4-2
(+15 kV air discharge) on one
input V in and one output V out
Figure 5. ESD response to IEC61000-4-2
(- 15 kV air discharge) on one
input V in and one output V out
Input
10V/d
Input
10V/d
Output
10V/d
Output
10V/d
200ns/d
200ns/d
Figure 6. Line capacitance versus applied
voltage
C
LINE
(pF)
28
26
24
22
20
18
16
14
12
V
(V)
LINE
10
0
1
2
3
4
5
3/6
0
0
0
0
-10
-10
-10
-5
-20
-20
-20
-10
-30
-30
-30
-15
-40
-40
-40
-20
-50
-50
-50
-25
-60
-60
-60
-30
-70
-70
-70
-80
-80
-80
-35
-90
-90
-90
-40
-100
-100
-100
-45
100k
100k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M
1G
1G
1G
100k
1M
10M
100M
1G
Input
10V/d
Output
10V/d
200ns/d
356213252.001.png 356213252.002.png 356213252.003.png 356213252.004.png 356213252.005.png 356213252.006.png 356213252.007.png 356213252.008.png
2 Ordering information scheme
EMIF08-VID01F2
2
Ordering information scheme
EMIF vv - xxx zz F y
EMI Filter
Number of lines
X: resistance (Ohms)
Z: capacitance value / 10 pF
or
Application (3 letters) and
Version (2 digits)
F: Flip chip
1: Pitch = 500 µm, Bump = 315 µm
2: Lead free Pitch = 500 µm, Bump = 315 µm
3
Package mechanical data flip chip
315 µm +/- 50
500µm +/-50
650µm +/- 65
250µm +/-50
3.92 mm +/-50µm
Figure 7. Marking
Figure 8. Foot print recommendation
Dot, ST Logo
xx = marking
z = packaging
location
yww = date code
Dimensions in µm
365
240
Copper pad Diameter :
250µm recommended , 300µm max
®
E
Solder stencil opening : 330µm
xxz
y ww
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
4/6
315 µm +/- 50
315 µm +/- 50
500µm +/-50
500µm +/-50
650µm +/- 65
250µm +/-50
250µm +/-50
3.92 mm +/-50µm
3.92 mm +/-50µm
Copper pad Diameter :
250µm recommended , 300µm max
®
®
Solder stencil opening : 330µm
xxz
y ww
xxz
y ww
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
356213252.009.png
EMIF08-VID01F2
4 Ordering information
Figure 9. Flip chip tape and reel specification
Dot identifying Pin A1 location
4 +/- 0.1
f 1.5 +/- 0.1
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
4
Ordering information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
EMIF08-VID01F2
GS
Flip Chip
6.8 mg
5000
7” Tape and reel
5
Revision history
Date
Revision
Changes
13-Jul-2005
1
Initial release.
11-Aug-2005
2
Fonts changed in Figures 7, 8, and 9
5/6
Dot identifying Pin A1 location
f 1.5 +/- 0.1
4 +/- 0.1
4 +/- 0.1
0.73 +/- 0.05
User direction of unreeling
356213252.010.png

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