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24C32
32K 5.0V I
2
C
Ô
Smart Serial EEPROM
FEATURES
PACKAGE TYPES
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150
PDIP
m
A at 5.5V
A0
1
8
V CC
A typical
• Industry standard two-wire bus protocol, I
- Standby current 1
m
A1
2
7
NC
2
C
Ô
compatible
- Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 Erase/Write cycles
guaranteed for High Endurance Block
- 1,000,000 E/W cycles guaranteed for
Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, ltered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus
for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
A2
3
6
SCL
V SS
4
5
SDA
SOIC
A0
1
8
V CC
A1
2
7
NC
A2
3
6
SCL
V SS
4
5
SDA
BLOCK DIAGRAM
- Commercial (C):
0˚C to +70˚C
- Industrial (I):
-40˚C to +85˚C
A0..A2
HV GENERATOR
DESCRIPTION
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM ARRAY
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM. This device has
been developed for advanced, low power applications
such as personal communications or data acquisition.
The 24C32 features an input cache for fast write loads
with a capacity of eight 8-byte pages, or 64 bytes. It
also features a xed 4K-bit block of ultra-high endur-
ance memory for data that changes frequently. The
24C32 is capable of both random and sequential reads
up to the 32K boundary. Functional address lines allow
up to 8 - 24C32 devices on the same bus, for up to 256K
bits address space. Advanced CMOS technology
makes this device ideal for low-power non-volatile code
and data applications. The 24C32 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package
PAGE LATCHES
I/O
SCL
Cache
SDA
YDEC
V CC
V SS
SENSE AMP
R/W CONTROL
2
C is a trademark of Philips Corporation.
Ó
1996 Microchip Technology Inc.
DS21061F-page 1
This document was created with FrameMaker404
I
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24C32
1.0
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
PIN FUNCTION TABLE
1.1
Maximum Ratings*
Name
Function
..................................................................................7.0V
All inputs and outputs w.r.t. V
CC
A0..A2
User Congurable Chip Selects
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins
SS
............... -0.6V to V
CC
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
..................................................³
4 kV
V
CC
+4.5V to 5.5V Power Supply
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specication is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
NC
No Internal Connection
TABLE 1-2:
DC CHARACTERISTICS
= +4.5V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
CC
Tamb = -40˚C to +85˚C
Parameter
Symbol
Min
Max
Units
Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage
V
IH
.7 Vcc
—
V
Low level input voltage
V
IL
—
.3 Vcc
V
Hysteresis of Schmitt Trigger inputs
V
HYS
.05 Vcc
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA
Input leakage current
I
LI
-10
10
m
AV
IN
= .1V
TO
V
CC
Output leakage current
I
LO
-10
10
m
AV
OUT
= .1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
—10
pF V
= 5.0V (Note 1)
Tamb = 25˚C, Fclk = 1 MHz
CC
Operating current
I
CC
W
RITE
—
—
3
150
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Read
m
A
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—5
m
AV
CC
= 5.5V, SCL = SDA = V
CC
(Note)
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
V HYS
SCL
T SU : STA
T HD : STA
T SU : STO
SDA
START
STOP
DS21061F-page 2
Ó
1996 Microchip Technology Inc.
V
*Notice:
V
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24C32
TABLE 1-3:
AC CHARACTERISTICS
STD. MODE
FAST MODE
Parameter
Symbol
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
—
100
—
400
kHz
Clock high time
T
HIGH
4000
—
600
—
ns
Clock low time
T
LOW
4700
—
1300
—
ns
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the rst clock
pulse is generated
START condition setup time T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—0
—ns
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission can
start
Output fall time from V
IH
min
T
OF
—
250
20 + 0.1
C
250
ns
(Note 1), C
B
£
100 pF
to V
IL
max
B
Input lter spike suppres-
sion (SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—5
—5
ms/page (Note 4)
Endurance
High Endurance Block
Rest of Array
—
—
10M
1M
—
—
10M
1M
—
—
cycles 25
C, Vcc = 5.0V, Block Mode
°
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undened region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
specications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
SP
and V
HYS
specication for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specic appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
I
FIGURE 1-2: BUS TIMING DATA
T F
T R
T HIGH
T LOW
SCL
T SU : STA
T HD : DAT
T SU : DAT
T SU : STO
T HD : STA
SDA
IN
T SP
T BUF
T AA
T AA
SDA
OUT
Ó
1996 Microchip Technology Inc.
DS21061F-page 3
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24C32
2.0 FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24C32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is dened as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C32 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.0 BUS CHARACTERISTICS
has been dened:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened ( Figure 3-1 ).
bus protocol
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note: The 24C32 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave (24C32) will leave the data line HIGH to
enable the master to generate the STOP condition.
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START CONDITION
ADDRESS
OR
ACKNOWLEDGE
VALID
DATA ALLOWED
TO CHANGE
STOP
CONDITION
DS21061F-page 4
Ó
1996 Microchip Technology Inc.
The following
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24C32
3.6
Device Addressing
acknowledge si gnal on the SDA line. Depending on the
state of the R/W bit, the 24C32 will select a read or write
operation.
A control byte is the rst byte received following the
start condition from the master device. The control byte
consists of a four bit control code; for the 24C32 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most signicant bit s o f
the word address. The last bit of the control byte (R/W)
denes the operation to be performed. When set to a
one a read operation is selected, and when set to a
zero a write operation is selected. The next two bytes
received dene the address of the rst data byte
( Figure 3-3 ). Because only A11..A0 are used, the upper
four address bits must be zeros. The most signicant bit
of the most signicant byte of the address is transferred
rst. Following the start condition, the 24C32 monitors
the SDA bus checking the device type identier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
2
1
0
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS BYTE 1
ADDRESS BYTE 0
1 010 A
2
A
1
A
0 R/W
0 000 A
11
A
10
A
9
A
8
A
7
·· · ···
A
0
SLAVE
ADDRESS
DEVICE
SELECT
BUS
Ó 1996 Microchip Technology Inc.
DS21061F-page 5
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