EMIF10-1K010F1.pdf

EMIF10-1K010F1

A.S.D. TM

EMI FILTER

INCLUDING ESD PROTECTION

MAIN APPLICATIONS

Where EMI filtering in ESD sensitive equipment is

required:

n Computers and printers

n Communication systems

n Mobile phones

n MCU Boards

DESCRIPTION

The EMIF10-1K010F1 is a highly integrated

device designed to suppress EMI / RFI noise in all

systems subjected to electromagnetic

interferences. The EMIF10 flip-chip packaging

means the package size is equal to the die size.

That's why EMIF10-1K010F1 is a very small

device.

Additionally, this filter includes an ESD protection

circuitry which prevents the protected device from

destruction when subjected to ESD surges up to

15 kV.

Flip Chip package

BENEFITS

n EMI symetrical (I/O) low-pass filter

n High efficiency in EMI filtering

n Very low PCB space consuming: 2.6 x 2.6 mm 2

n Very thin package: 0.65 mm

n High efficiency in ESD suppression on both input

& output PINS (IEC61000-4-2 level 4).

n High reliability offered by monolithic integration

n High reducing of parasitic elements through in-

tegration & wafer level packaging.

PIN CONFIGURATION (Ball Side)

ABCDE

BASIC CELL CONFIGURATION

Low-passfilter

GND

Input

Output

GND GND

I10

O10

Cinput = 100pF

TM : ASD is a trademark of STMicroelectronics.

February 2001 - Ed: 2C

1/13

GND

Ri/o = 1k

EMIF10-1K010F1

COMPLIES WITH FOLLOWING STANDARD:

IEC61000-4-2 level 4 15 KV

(air discharge)

8 kV

(contact discharge)

on input & output pins

MIL STD 883C - Method 3015-6 Class 3

Filtering Behavior

ESD response to IEC61000-4-2 (16kV Air Dis-

charge)

S21 (dB)

-10

-20

V(in1)

-30

-40

V(out1)

-50

100

1,000

frequency (MHz)

Capacitance versus reverse applied voltage.

C(pF)

100

F=1MHz

Vosc=30mV

VR(V)

2/13

EMIF10-1K010F1

ABSOLUTE MAXIMUM RATINGS (T amb =25°C)

Symbol

Parameter and test conditions

Value

Unit

V PP

ESD discharge IEC61000-4-2, air discharge

ESD discharge IEC61000-4-2, contact discharge

MIL STD 883C Method 3015-6

T j

Junction temperature

125

°C

T op

Operating temperature range

-40 to + 85

°C

T stg

Storage temperature range

-55 to +150

°C

ELECTRICAL CHARACTERISTICS (T amb = 25°C)

Symbol

Parameters

V BR

Breakdown voltage

I RM

Leakage current @ V RM

V RM

Stand-off voltage

V CL

Clamping voltage

V CL

V BR

V RM

R d

Dynamic impedance

I PP

Peak pulse current

R I/O

Series resistance between Input &

Output

slope : 1 / R d

C in

Input capacitance per line

Symbol

Test conditions

Min

Typ

Max

Unit

V BR

I R = 1mA

I RM

V RM = 3V per line

500

R d

I PP = 10A, t p = 2.5

s (see note 1)

R I/O

900

1000

1100

Cline

At 0V bias

100

120

Note 1 : To calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on page 5.

3/13

EMIF10-1K010F1

TECHNICAL INFORMATION

FREQUENCY BEHAVIOR

Fig. A1: Frequency response curve

The EMIF10-1K010F1 is firstly designed as an

EMI / RFI filter. This low-pass filter is characterized

by the following parameters:

- Cut-off frequency

- Insertion loss

- High frequency

S21 (dB)

-10

-20

Figure A1 gives these parameters, in particular the

signal rejection at the GSM frequency:

- 25dB @ 900Mhz

- 14dB @ 1800Mhz

-30

-40

-50

100

1,000

frequency (MHz)

Fig. A2: Measurements conditions

TEST BOARD

out1

in1

4/13

EMIF10-1K010F1

ESD PROTECTION

In addition with the filtering the EMIF10-1K010F1 is particularly optimized to perform ESD protection.

ESD protection is based on the use of device which clamps at:

VVRI

=+×

d pp

This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by

the first stage S1 and then its remaining overvoltage is applied to the second stage through the resis-

tor R. Such a configuration makes the output voltage very low at the Vout level.

Fig. A3: ESD clamping behavior

R=1k

Rload

Vinput Voutput

Vbr

ESD Surge

EMIF10-1k010F1

Device

to be

protected

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and

Rload>>Rd, it gives these formulas:

Vinpout

= ×

RV RV

+×

Voutput

RV R V

+×

The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV,

Rg=330

) and Vbr=7V (typ.) give:

Vinput = 31.24V

Voutput = 7.03V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low

current involved after the series resistance R.

5/13

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