EMIF10-COM01F2.pdf

EMIF10-COM01F2

IPAD™

EMI FILTER

INCLUDING ESD PROTECTION

MAIN PRODUCT CHARACTERISTICS

EMI filtering and ESD protection for:

■

Computers and printers

■

Communication systems

Mobile phones

■

DESCRIPTION

The EMIF10-COM01F2 is a highly integrated

device designed to suppress EMI / RFI noise in all

systems subjected to electromagnetic interfer-

ences. The EMIF10 Flip-Chip packaging means

the package size is equal to the die size.

Additionally, this filter includes an ESD protection

circuitry which prevents the protected device from

destruction when subjected to ESD surges up to

15 kV.

Flip-Chip

(25 Bumps)

Table 1: Order Code

Part Number

Marking

EMIF010-COM01F2

Figure 1: Pin Configuration (Ball side)

BENEFITS

■

EMI symmetrical (I/O) low-pass filter

EDC

■

Lead free package

Very low PCB space consuming: < 7mm 2

■

Very thin package: 0.65 mm

I10

■

High efficiency in ESD suppression on both

input & output pins

GND

■

High reliability offered by monolithic integration

010

COMPLIES WITH THE FOLLOWING STANDARDS:

IEC61000-4-2 level 4

15kV (air discharge)

8kV (contact discharge)

Figure 2: Basic cell configuration

Low-pass Filter

Input

Output

Ω

C = 45 pF

line

I/O

TM: IPAD is a trademark of STMicroelectronics.

December 2004

REV. 1

1/7

R = 200

EMIF10-COM01F2

Table 2: Absolute Ratings (T amb = 25°C)

Symbol

Parameter and test conditions

Value

Unit

V PP

ESD discharge IEC61000-4-2, air discharge

ESD discharge IEC61000-4-2, contact discharge

T j

Junction temperature

125

°C

T op

Operating temperature range

- 40 to + 85

°C

T stg

Storage temperature range

- 55 to + 150

°C

Table 3: Electrical Characteristics (T amb = 25°C)

Symbol Parameter

V BR Breakdown voltage

I RM Leakage current @ V RM

V RM Stand-off voltage

V CL

Clamping voltage

V CL

V BR

V RM

R d

Dynamic impedance

I PP Peak pulse current

R I/O Series resistance between Input &

Output

C line Input capacitance per line

slope : 1 / R d

Symbol

Test conditions

Min.

Typ.

Max.

Unit

V BR

I R = 1 mA

I RM

V RM = 3V per line

500

R d

I PP = 10A, t p = 2.5µs

Ω

R I/O

180

200

220

Ω

C line

At 0V bias

t LH

Vinput = 2.8V Rload = 100k

Ω

2/7

EMIF10-COM01F2

Figure 3: S21(db) attenuation measurement

Figure 4: Analog crosstalk

EMIF10-COM01F2: Typical A1/A2 crosstalk measurement

EMIF10-COM01F2: Typical S21(dB) measurement on line I10/O10

0.00

-5.00

-10.00

-15.00

-10.00

-20.00

-15.00

-25.00

-30.00

-20.00

-35.00

-25.00

-40.00

-45.00

-30.00

-50.00

-35.00

-55.00

-60.00

-40.00

-65.00

-45.00

-70.00

-75.00

-50.00

-80.00

1.0M

3.0M

10.0M 30.0M

100.0M 300.0M

1.0G

3.0G

1.0M

3.0M

10.0M 30.0M

100.0M 300.0M

1.0G

3.0G

f/Hz

Note: Spikes at high frequencies are induced by the PCB layout

Figure 5: ESD response to IEC61000-4-2

(+15kV air discharge) on one input V(in) and on

one output (Vout)

Figure 6: ESD response to IEC61000-4-2 (-15kV

air discharge) on one input V(in) and on one

output (Vout)

V(in1)

V(out1)

Figure 7: Rise time measurement

EMIF10-COM01F2

Out

Vout

Square signal

Generator Vc = 2.8V

Vin

100k Vout

Vin

3/7

EMIF10-COM01F2

Figure 8: Capacitance versus reverse applied

voltage

C(pF)

F=1MHz

Vosc=30mV

VR(V)

Figure 9: Aplac model

200R

out

Demif10 model

BV = 7

IBV = 1m

CJO = 25p

M = 0.3333

RS = 1

VJ = 0.6

TT = 100n

MODEL = demif10

sub

PCB grounding recommendations

In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to

implement microvias (100 µm dia.) between the GND bumps and the GND layer. GND bumps can be con-

m dia.) in both

sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and

thus parasitic inductances. In addition, we recommend to have GND plane wherever possible.

4/7

nected together in PCB layer 1, and in addition, if possible, use through hole vias (200

EMIF10-COM01F2

Figure 10: Ordering Information Scheme

EMIF yy - xxx zz Fx

EMI Filter

Number of lines

Information

x = resistance value (Ohms)

z = capacitance value / 10(pF)

3 letters = application

2 digits = version

Package

F = Flip-Chip

x = 1: 500µm, Bump = 315µm

= 2: Leadfree Pitch = 500µm, Bump = 315µm

= 3: Leadfree Pitch = 400µm, Bump = 250µm

Figure 11: FLIP-CHIP Package Mechanical Data

500µm ± 50

650µm ± 65

315µm ± 50

2.64mm ± 50µm

Figure 12: Foot print recommendations

Figure 13: Marking

5 45

400

Copper pad Diameter :

250µm recommended , 300µm max

Dot, ST logo

xx = marking

yww = datecode

(y = year

ww = week)

Solder stencil opening : 330µm

Solder mask opening recommendation :

340µm min for 315µm copper pad diameter

All dimensions in µm

5/7

z = packaging location

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