74HC_HCT190_CNV_2.pdf

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT190

Presettable synchronous BCD

decade up/down counter

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous BCD decade

up/down counter

74HC/HCT190

FEATURES

Overflow/underflow indications are provided by two t ype s

of outputs, the terminal count (TC) and ripple clock (RC).

The TC output is normally LOW and goes HIGH when a

circuit reaches zero in the count-down mode or reaches “9”

in the count-up-mode. The TC output will remain HIGH

until a state chang e occurs, either by counting or

presetting, or until U/D is changed. Do not use the TC

output as a clock signal because it is subject to decod ing

spikes. The TC signal is used i nte rnally to ena ble t he RC

output. When TC is HIGH and CE is LOW, the RC output

follows the clock pulse (CP). This feature simplifies the

design of multistage counters as shown in Figs 5 and 6.

Synchronous reversible counting

Asynchronous parallel load

Count enable control for synchronous expansion

Single up/down control input

Output capability: standard

I CC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT190 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT190 are asynchronously presettable

up/down BCD decade counters. They contain four

master/slave flip-flops with internal gating and steering

logic to provide asynchronous preset and synchronous

count-up and count-down operation.

In Fig.5, each RC output is used as the clock input to the

next higher stage. It is only necessary to inhibit the first

stag e to preve nt c ounting in all stages, since a HIGH on

CE inhibits the RC output pulse as indicated in the function

table. The timing skew between state changes in the first

and last stages is represented by the cumulative delay of

the clock as it ripples through the preceding stages. This

can be a disadvantage of this configuration in some

applications.

Asynchronous parallel load capability permits the counter

to be preset to any desired number. Information present on

the parallel data inputs (D 0 to D 3 ) is loaded into the c oun ter

and appears on the outputs when the parallel load (PL)

input is LOW. As indicated in the function table, this

operation overrides the counting function.

Fig.6 shows a method of causing sta te changes to occur

simultaneously in all stages. The RC outputs propagate

the carry/borrow signals in ripple fashion and all clock

inputs are driven in parallel. In this configuration the

duration of the clock LOW state must be long enough to

allow the negative-going edge of the carry/borrow signal to

ripple through to the last stage before the clock goes

HIGH. Since the RC output of any package goes HIGH

shortly after its CP input goes HIGH there is no such

restriction on the HIGH-state duration of the clock.

Cou nting is inhibit ed b y a HIGH level on the count enable

(CE) input. When CE is LOW internal state changes are

initiated synchronously by the L OW-to-HIGH transition of

the clock input. The up/down (U/D) input signal determines

the d irec tion of counting as indicated in the function table.

The CE input may go LOW when t he c lock is in either

state, however, the LOW-to-HIGH CE transiti on must

occur only when the clock is HIGH. Also , the U/D input

should be changed only when either CE or CP is HIGH.

In Fig.7, the configuration shown avoids ripple delays and

their associated restrictions. Combining the TC signals

from all the preceding stages forms the CE input for a

given stage. An enable must be included in each carry

gate in order to inhibit counting . Th e TC output of a given

stage it not affected by its own CE signal therefore the

simple inhibit scheme of Figs 5 and 6 does not apply.

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous BCD decade

up/down counter

74HC/HCT190

QUICK REFERENCE DATA

GND = 0 V; T amb =25 ° C; t r =t f = 6 ns

TYPICAL

SYMBOL

PARAMETER

CONDITIONS

UNIT

HCT

t PHL / t PLH

propagation delay CP to Q n

C L = 15 pF; V CC = 5 V

f max

maximum clock frequency

MHz

C I

input capacitance

3.5

C PD

power dissipation capacitance per flip-flop notes 1 and 2

Notes

1. C PD is used to determine the dynamic power dissipation (P D in

W):

P D =C PD ´

V CC 2

f i + å

(C L ´

V CC 2

f o ) where:

f o ) = sum of outputs

C L = output load capacitance in pF

V CC = supply voltage in V

2. For HC the condition is V I = GND to V CC

For HCT the condition is V I = GND to V CC - 1.5 V

f i = input frequency in MHz

f o = output frequency in MHz

(C L ´

V CC 2

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information” .

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous BCD decade

up/down counter

74HC/HCT190

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

3, 2, 6, 7

Q 0 to Q 3

ﬂip-ﬂop outputs

C E

count enable input (active LOW)

U/D

up/down input

GN D

ground (0 V)

parallel load input (active LOW)

terminal count output

ripple clock output (active LOW)

clock input (LOW-to-HIGH, edge-triggered)

15, 1, 10, 9

D 0 to D 3

data inputs

V CC

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Presettable synchronous BCD decade

up/down counter

74HC/HCT190

Fig.4 Functional diagram.

FUNCTION TABLE

OPERATING MODE

INPUTS

OUTPUTS

U/D

D n

Q n

parallel load

count up

count down

hold (do nothing)

no change

TC AND RC FUNCTION TABLE

INPUTS

TERMINAL COUNT STATE

OUTPUTS

U/D

Q 0

Q 1

Q 2

Q 3

Notes

1. H = HIGH voltage level

L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

X = don’t care

= LOW-to-HIGH CP transition

= one LOW level pulse

= TC goes LOW on a LOW-to-HIGH CP transition

December 1990

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