74HC_HCT238_CNV_2.pdf

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3-to-8 line decoder/demultiplexer
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT238
3-to-8 line decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
21701175.006.png
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
FEATURES
provide 8 mutually exclusive active HIGH outputs
(Y 0 to Y 7 ).
Th e “23 8” features three enable inputs: two active LOW
(E 1 and E 2 ) a nd one ac tive HIGH (E 3 ). Every output will be
LOW unless E 1 and E 2 are LOW and E 3 is HIGH.
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
·
Demultiplexing capability
·
Multiple input enable for easy expansion
·
Ideal for memory chip select decoding
·
Active HIGH mutually exclusive outputs
·
Output capability: standard
·
I CC category: MSI
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A 0 , A 1 , A 2 ) and when enabled,
QUICK REFERENCE DATA
GND = 0 V; T amb =25
C; t r =t f = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t PHL/ t PLH
propagation delay
C L = 15 pF; V CC =5 V
A n to Y n
14
18
ns
E 3 to Y n
16
20
ns
E n to Y n
17
21
ns
C I
input capacitance
3.5
3.5
pF
C PD
power dissipation capacitance per package notes 1 and 2
72
76
pF
Notes
1. C PD is used to determine the dynamic power dissipation (P D in m W):
P D =C PD ´
V CC 2
´
f i + å
(C L ´
V CC 2
´
f o ) where:
f o ) = sum of outputs
C L = output load capacitance in pF
V CC = supply voltage in V
2. For HC the condition is V I = GND to V CC
For HCT the condition is V I = GND to V CC -
f i = input frequency in MHz
f o = output frequency in MHz
å
(C L ´
V CC 2
´
1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information” .
December 1990
2
°
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Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 2, 3
A 0 t o A 2
address inputs
4, 5
E 1 , E 2
enable inputs (active LOW)
6
E 3
enable input (active HIGH)
8
GND
ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7 Y 0 to Y 7
outputs (active HIGH)
16
V CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
(a)
(b)
Fig.3 IEC logic symbol.
December 1990
3
21701175.008.png 21701175.009.png 21701175.001.png 21701175.002.png 21701175.003.png
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUTS
E 1
E 2
E 3
A 0
A 1
A 2
Y 0
Y 1
Y 2
Y 3
Y 4
Y 5
Y 6
Y 7
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
December 1990
4
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Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
74HC/HCT238
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” .
Output capability: standard
I CC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t r =t f = 6 ns; C L = 50 pF
T amb (
°
C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
V CC
(V)
+
25
-
40 to
+
85
-
40 to
+
125
min. typ. max. min. max. min. max.
t PHL / t PLH propagation delay
A n to Y n
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t PHL / t PLH propagation delay
E 3 to Y n
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
t PHL / t PLH p ro pagation delay
E n to Y n
50
18
14
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
t THL / t TLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
December 1990
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