attiny13.pdf

Features

• High Performance, Low Power AVR ® 8-Bit Microcontroller

Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Througput at 20 MHz

High Endurance Non-volatile Memory segments

– 1K Bytes of In-System Self-programmable Flash program memory

– 64 Bytes EEPROM

– 64 Bytes Internal SRAM

– Write/Erase cyles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (see page 6 )

– Programming Lock for Self-Programming Flash & EEPROM Data Security

Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

– 20-pad MLF: Six Programmable I/O Lines

Operating Voltage:

– 1.8 - 5.5V for ATtiny13V

– 2.7 - 5.5V for ATtiny13

Speed Grade

– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

Industrial Temperature Range

Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 240µA

– Power-down Mode:

< 0.1µA at 1.8V

8-bit

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

ATtiny13

ATtiny13V

Not recommended for new

designs. Use ATtiny13A.

Rev. 2535I–AVR–05/08

1. Pin Configurations

Figure 1-1. Pinout ATtiny13/ATtiny13V

8-PDIP/SOIC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

20-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

10-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

ATtiny13

2535I–AVR–05/08

ATtiny13

1.1 Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

GND

Ground.

1.1.3

Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13 as listed on page 54 .

1.1.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page

115 . Shorter pulses are not guaranteed to generate a reset.

The reset pin can also be used as a (weak) I/O pin.

2535I–AVR–05/08

2. Overview

The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

8-BIT DATABUS

STACK

POINTER

CALIBRATED

WATCHDOG

OSCILLATOR

INTERNAL

OSCILLATOR

SRAM

WATCHDOG

TIMER

TIMING AND

CONTROL

VCC

PROGRAM

COUNTER

MCU CONTROL

GND

MCU STATUS

PROGRAM

FLASH

TIMER/

COUNTER0

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

CONTROL

LINES

ALU

DATA

EEPROM

STATUS

ADC /

ANALOG COMPARATOR

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT B DRIVERS

RESET

CLKI

PB0-PB5

ATtiny13

2535I–AVR–05/08

ATtiny13

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64

bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-

isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-

channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-

ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The

Power-down mode saves the register contents, disabling all chip functions until the next Inter-

rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules

except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny13 AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

2535I–AVR–05/08

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