BUK581-100A_2.pdf

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Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
SYMBOL PARAMETER
MAX.
UNIT
logic level field-effect power
transistor in a plastic envelope
V DS
Drain-source voltage
100
V
suitable for surface mount
I D
Drain current (DC)
0.9
A
applications.
P tot
Total power dissipation
1.5
W
The device is intended for use in
T j
Junction temperature
150
˚C
automotive and general purpose
R DS(ON)
Drain-source on-state
0.90
W
switching applications.
resistance;
V GS = 5 V
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
4
d
1
gate
2
drain
3
source
g
4
drain (tab)
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DS
Drain-source voltage
-
-
100
V
V DGR
Drain-gate voltage
R GS = 20 k
W
-
100
V
±
V GS
Gate-source voltage
-
-
15
V
I D
Drain current (DC)
T amb = 25 ˚C
-
0.9
A
I D
Drain current (DC)
T amb = 100 ˚C
-
0.6
A
I DM
Drain current (pulse peak value)
T amb = 25 ˚C
-
3.6
A
P tot
Total power dissipation
T amb = 25 ˚C
-
1.5
W
T stg
Storage temperature
-
- 55
150
˚C
T j
Junction Temperature
-
-
150
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
R th j-b
From junction to board 1
Mounted on any PCB
-
50
-
K/W
R th j-amb
From junction to ambient
Mounted on PCB of Fig.17
-
-
85
K/W
1 Temperature measured 1-3 mm from tab.
January 1998
1
Rev 1.000
Logic level FET
22889540.009.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
STATIC CHARACTERISTICS
T j = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA
100
-
-
V
voltage
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 0.1 mA
1.0
1.5
2.0
V
I DSS
Zero gate voltage drain current V DS = 100 V; V GS = 0 V;
-
1
10
A
m
I DSS
Zero gate voltage drain current V DS = 100 V; V GS = 0 V; T j = 125 ˚C
-
0.1
1.0
mA
I GSS
Gate source leakage current
V GS =
±
15 V; V DS = 0 V
-
10
100
nA
R DS(ON)
Drain-source on-state
V GS = 5 V; I D = 0.9 A
-
0.51 0.90
W
resistance
DYNAMIC CHARACTERISTICS
T j = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
g fs
Forward transconductance
V DS = 25 V; I D = 0.9 A
1
1.8
-
S
C iss
Input capacitance
V GS = 0 V; V DS = 25 V; f = 1 MHz
-
180
300
pF
C oss
Output capacitance
-
45
60
pF
C rss
Feedback capacitance
-
16
25
pF
t d on
Turn-on delay time
V DD = 30 V; I D = 3 A;
-
6
10
ns
t r
Turn-on rise time
V GS = 5 V; R GS = 50
W
;
-
45
55
ns
t d off
Turn-off delay time
R gen = 50
W
-
15
25
ns
t f
Turn-off fall time
-
20
30
ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T j = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I DR
Continuous reverse drain
-
-
-
0.9
A
current
I DRM
Pulsed reverse drain current
-
-
-
3.6
A
V SD
Diode forward voltage
I F = 0.9 A; V GS = 0 V
-
0.85
1.1
V
t rr
Reverse recovery time
I F = 0.9 A; -dI F /dt = 100 A/
m
s;
-
40
-
ns
Q rr
Reverse recovery charge
V GS = -10 V; V R = 30 V
-
100
-
nC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
W DSS
Drain-source non-repetitive
I D = 0.9 A; V DD
£
25 V;
-
-
10
mJ
unclamped inductive turn-off
V GS = 5 V; R GS = 50
W
; T amb = 25 ˚C
energy
January 1998
2
Rev 1.000
Logic level FET
22889540.010.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
10
ID / A
BUK581-100A
tp = 100 us
1
1 ms
10 ms
0.1
DC
100 ms
1 s
10 s
0
20
40
60
80
100
120
140
0.01
1
10
100
Tamb / C
VDS / V
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T amb )
Fig.4. Safe operating area T amb = 25 ˚C
I D & I DM = f(V DS ); I DM single pulse; parameter t p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
ID / A
BUK581-100A
5
10
4.5
5
4
4
3
3.5
2
3
1
VGS / V = 2.5
0
20
40
60
80
100
120
140
0
0
2
4
6
8
10
Tamb / C
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100
×
I D /I D 25 ˚C = f(T amb ); conditions: V GS
³
5 V
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
Zth j-amb / (K/W)
BUKX81
RDS(ON) / Ohm
BUK581-100A
1E+02
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
D =
2.5
3
3.5
4
0.5
0.2
0.1
0.05
0.02
1E+01
1E+00
4.5
t p
t p
P
D =
D
T
5
1E-01
VGS / V = 10
T
t
1E-02
1E-07
1E-05
1E-03
1E-01
1E+01
1E+03
0
1
2
3
4
5
t / s
ID / A
Fig.3. Transient thermal impedance.
Z th j-amb = f(t); parameter D = t p /T
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
January 1998
3
Rev 1.000
Logic level FET
22889540.011.png 22889540.012.png 22889540.001.png 22889540.002.png 22889540.003.png 22889540.004.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
ID / A
BUK581-100A
VGS(TO) / V
5
Tj / C = 25
max.
2
4
150
typ.
3
min.
1
2
1
0
0
0
1
2
3
4
5
-60 -40 -20 0
20 40 60 80 100 120 140
Tj / C
VGS / V
Fig.7. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.10. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 0.1 mA; V DS = V GS
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
gfs / S
BUK581-100A
1E-02
ID / A
SUB-THRESHOLD CONDUCTION SIZE 1
1E-03
1E-04
2 %
typ
98 %
1E-05
1E-06
0
1
2
3
4
5
1E-07
0
0.4
0.8
1.2
1.6
2
2.4
ID / A
VGS / V
Fig.8. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
Fig.11. Sub-threshold drain current.
I D = f(V GS ); conditions: T j = 25 ˚C; V DS = V GS
2.0
a
Normalised RDS(ON) = f(Tj)
1000
C / pF
BUK581-100A
1.5
Ciss
1.0
100
0.5
Coss
Crss
0
10
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
0
10
20
30
40
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j ); I D = 0.9 A; V GS = 5 V
Fig.12. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
January 1998
4
Rev 1.000
Logic level FET
22889540.005.png 22889540.006.png
Philips Semiconductors
Product Specification
PowerMOS transistor
BUK581-100A
VGS / V
BUK581-100A
WDSS%
Normalised Avalanche Energy
10
9
8
7
6
5
4
3
2
1
0
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS / V =20
80
0
2
4
6
8
10
20
40
60
80
100
120
140
QG / nC
Tamb/ C
Fig.13. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); conditions: I D = 0.9 A; parameter V DS
Fig.15. Normalised avalanche energy rating.
W DSS % = f(T amb ); conditions: I D = 0.9 A
5
IF / A
BUK581-100A
+
VDD
4
L
Tj / C = 150
25
VDS
3
-
VGS
-ID/10 0
2
0
T.U.T.
1
RGS
R 01
shunt
0
0
0.5
1
1.5
VSDS / V
Fig.16. Avalanche energy test circuit.
Fig.14. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
W DSS =
0.5
×
LI 2
×
BV DSS /(
BV DSS -
V DD )
January 1998
5
Rev 1.000
Logic level FET
22889540.007.png 22889540.008.png

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