tda2579c.pdf

INTEGRATED CIRCUITS

DATA SHEET

TDA2579C

Synchronization circuit with

synchronized vertical divider

system for 60 Hz

Preliminary specication

File under Integrated Circuits, IC02

January 1994

Philips Semiconductors

Philips Semiconductors

Preliminary specication

Synchronization circuit with synchronized

vertical divider system for 60 Hz

TDA2579C

FEATURES

Vertical part

Synchronization and horizontal part

f V = 60 Hz (M) system

Horizontal sync separator and noise inverter

Vertical synchronization pulse separator without

external components and two integration times

Horizontal oscillator

Zener diode reference voltage source for the vertical

sawtooth generator and vertical comparator

Horizontal output stage

Horizontal phase detector (sync to oscillator)

Divider system with three different reset enable windows

Triple current source in the phase detector with

automatic selection

Synchronization is set to 528 divider ratio when no

vertical sync pulse and no video transmitter is identified

Normal phase detector time constant is increased to fast

during the vertical blanking period (external switching for

VTR conditions not necessary)

Divider window is forced to wide window when a vertical

sync pulse is detected within the window provided by

reset divider and end of vertical blanking period, on

condition that the voltage on pin 18 is

Slow phase detector time constant and gated sync pulse

operation are automatically switched on by an internal

sync pulse noise level detection circuit

1.2 V

Divider ratio is 528 (f V = 60 Hz) for DC signal on pin 5

Linear negative-going sawtooth generated via the

divider system (no frequency adjustment)

Fast phase detector time is switched on for locking

Time constant externally switchable

Comparator with low DC level feedback signal

Inhibit of horizontal phase detector and video transmitter

identification circuit during equalizing pulses and vertical

sync pulse

Output stage driver

f V = 60 Hz identification output combined with mute

function

Inhibit of horizontal phase detector during separated

vertical sync pulse

Start of vertical blanking is shifted to the start of the

pre-equalizing pulses when the divider ratio is between

522 and 528 lines per picture

Second phase detector for storage compensation of the

line output stage

Guard circuit which generates the vertical blanking

pulse level on the sandcastle output pin 17 when the

feedback level at pin 2 is not within the specified limits.

3-level sandcastle pulse generator

Automatic adaption of the burst key pulse width

Video transmitter identification circuit

Stabilizer and supply circuit for starting the horizontal

oscillator and output stage directly from the mains

rectifier

GENERAL DESCRIPTION

The TDA2579C is an integrated circuit generating all

requirements for synchronization of its horizontal oscillator

and output stage plus those of the vertical part which

comprises a divider system, sawtooth generator,

comparator and output stage.

The TDA2579C is almost identical to the TDA2579B.

It is optimized for the M (60 Hz) TV system.

Horizontal output current with constant duty factor value

of 55%

Duty factor of the horizontal output pulse is 55% when

the horizontal flyback pulse is absent.

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

TDA2579C

DIL

plastic

SOT102

January 1994

Philips Semiconductors

Preliminary specication

Synchronization circuit with synchronized

vertical divider system for 60 Hz

TDA2579C

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

I 16

minimum required current for starting

horizontal oscillator and output stage

6.2

V 10

main supply voltage

I 10

supply current

Input signals

V 5-9

sync pulse input amplitude

0.05

I 12

horizontal yback pulse input current

0.2

V 2

vertical comparator input voltage

AC (peak-to-peak value)

0.8

Output signals

V 11

horizontal output voltage

(open collector)

I 11 = 25 mA

0.5

V 1

vertical output stage driver

(emitter follower)

I 1 = 1.5 mA

V 17

sandcastle output voltage levels

burst key

9.8

horizontal blanking

4.5

vertical blanking

2.5

V IDEO TRANSMITTER IDENTIFICATION OUTPUT ; note 1

V 13

output voltage

no sync pulse present

0.32

I 13

output current

no sync pulse present

V 13

output voltage

sync pulse present;

divider ratio <576

7.6

Note

1. Open collector loaded with external resistor to positive supply.

January 1994

I 6.2 mA

12 V

6.8 m F

m F

video

signal

input

150 pF

1.2 k

2.7 nF

1 k

68 nF

3 3 k

4.7 k

2.2

VERTICAL/

HORIZONTAL

SYNC

SEPARATOR

SYNC PULSE

NOISE LEVEL

DETECTOR

START

CIRCUIT

STABILIZER

NOISE

DETECTOR

R =

5.6 k

PHASE

DETECTOR

j 1

m F

NOISE

INVERTER

j 1

REFERENCE

ANTITOP

HORIZONTAL

OSCILLATOR

SUPPLY

SWITCH

COINCIDENCE

DETECTOR

GATING

47 nF

DIVIDER

VERTICAL

BLANKING

BURST

KEY

j 2

REFERENCE

HORIZONTAL

OUTPUT

horizontal

drive

VIDEO

TRANSMITTER

IDENTIFICATION

mute

60 Hz

6.8 k

15 k

VERTICAL

ZENER

REFERENCE

VERTICAL

GUARD

CIRCUIT

SANDCASTLE

OUTPUT

FLYBACK

PULSE

PROTECTION

TOO LOW

CURRENT

PROTECTION

to pin 16

12 V

VERTICAL/

OSCILLATOR

SAWTOOTH

GENERATOR

VERTICAL

COMPARATOR

VERTICAL

OUTPUT

PULSE

WIDTH

MODULATOR

PHASE

DETECTOR

j 2

TDA2579C

MGA791

150 k

150 nF

4.7 nF

100 nF

vertical

feedback

220 k

to vertical deflection

current measuring resistor

vertical

drive

sandcastle

output

flyback pulse

input

Fig.1 Block diagram.

Philips Semiconductors

Preliminary specication

Synchronization circuit with synchronized

vertical divider system for 60 Hz

TDA2579C

PINNING

SYMBOL

DESCRIPTION

V OUT

vertical driver output

vertical feedback input

SAW

vertical sawtooth generator

VDC

vertical deection current output

OUT

DET

VID

video signal input

CSL

slicing level storage capacitor

SAW

STAB

RSL

slicing level resistor

j 1

phase detector

j 1

VDC

OSC

GND

ground (0 V)

VID

TDA2579C

SHIFT

V P

10 main supply voltage (+12 V)

CSL

MUTE

H OUT

horizontal driver output

RSL

FLYB

12 horizontal yback pulse input

OUT

MUTE

13 mute output

GND

V P

H SHIFT

14 horizontal picture shift capacitor

MGA790

H OSC

15 horizontal oscillator frequency

setting

STAB

16 start circuit stabilizer input

17 sandcastle output

Fig.2 Pin configuration.

DET

18 coincidence detector output

FUNCTIONAL DESCRIPTION

The TDA2579C generates both horizontal and vertical

drive signals, a 3-level sandcastle output pulse, a

transmitter identification signal and 60 Hz window

information.

divider system for generating the vertical sawtooth at

pin 3. Thus no vertical frequency adjustment is required.

The circuit operation is restricted to the M (f V = 60 Hz)

system.

The horizontal oscillator and horizontal output stage

functions are started via the supply current into pin 16.

The required current has a typical value of 5 mA which can

be taken directly from the mains rectifier. The horizontal

output transistor at pin 11 is not conducting until the supply

current at pin 16 has reached its typical value. The starting

circuit has a hysteresis of approximately 1 mA. The

horizontal output current of pin 11 starts at a duty cycle of

60%. All other IC functions are enabled via the main supply

voltage on pin 10.

The pin 16 supply system enables slaved synchronized

switch mode systems in which the horizontal output signal

of the TDA2579C is used as master signal. In such a

system the 12 V supply (main supply at pin 10) can be

generated by the line output stage.

An internal Zener diode reference voltage is used for the

vertical processing part. The IC embodies a synchronized

Vertical part (pins 1, 2, 3 and 4)

The IC embodies a synchronized divider system for

generating the vertical sawtooth at pin 3. The divider

system has an internal frequency doubling circuit, thus the

horizontal oscillator is operating at its nominal line

frequency and one line period equals 2 clock pulses.

No vertical frequency adjustment is required due to the

divider system. The divider system operates with

3 different reset windows for maximum

interference/disturbance protection.

The windows are activated via an up/down counter.

The counter increases its value by 1 each time the

separated vertical sync pulse is within the window being

searched. The count is reduced by 1 when the vertical

sync pulse is not present.

The reset of the counter system (clock pulse 0) is at half a

line period after the start of the vertical pulse at pin 5.

January 1994

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