80C51-Family-programming.pdf

Philips Semiconductors

80C51 Family

80C51 family programmer’s guide

and instruction set

PROGRAMMER’S GUIDE AND INSTRUCTION SET

initializes the stack pointer to location 07H, and it is incremented

once to start from location 08H, which is the first register (R0) of

the second register bank. Thus, in order to use more than one

of the RAM where it is not used for data storage (i.e., the higher

part of the RAM).

2. Bit Addressable Area: 16 bytes have been assigned for this

segment, 20H-2FH. Each one of the 128 bits of this segment can

be directly addressed (0-7FH). The bits can be referred to in two

ways, both of which are acceptable by most assemblers. One

way is to refer to their address (i.e., 0-7FH). The other way is

with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be

referred to as bits 20.0-20.7, and bits 8-FH are the same as

21.0-21.7, and so on. Each of the 16 bytes in this segment can

also be addressed as a byte.

3. Scratch Pad Area: 30H through 7FH are available to the user as

data RAM. However, if the stack pointer has been initialized to

this area, enough bytes should be left aside to prevent SP data

destruction.

Memory Organization

Program Memory

The 80C51 has separate address spaces for program and data

memory. The Program memory can be up to 64k bytes long. The

lower 4k can reside on-chip. Figure 1 shows a map of the 80C51

program memory.

The 80C51 can address up to 64k bytes of data memory to the chip.

The MOVX instruction is used to access the external data memory.

The 80C51 has 128 bytes of on-chip RAM, plus a number of Special

Function Registers (SFRs). The lower 128 bytes of RAM can be

accessed either by direct addressing (MOV data addr) or by indirect

addressing (MOV @Ri). Figure 2 shows the Data Memory

organization.

Direct and Indirect Address Area

The 128 bytes of RAM which can be accessed by both direct and

indirect addressing can be divided into three segments as listed

below and shown in Figure 3.

1. Register Banks 0-3: Locations 0 through 1FH (32 bytes). The

device after reset defaults to register bank 0. To use the other

Figure 2 shows the different segments of the on-chip RAM.

FFFF

60k

BYTES

EXTERNAL

64k

BYTES

EXTERNAL

1000

AND

0FFF

4k BYTES

INTERNAL

0000

SU00567

Figure 1. 80C51 Program Memory

1997 Sept 18

Philips Semiconductors

80C51 Family

80C51 family programmer’s guide

and instruction set

0FFF

INTERNAL

64k

BYTES

EXTERNAL

SFRs

DIRECT ADDRESSING

ONLY

AND

DRIECT AND INDIRECT

ADDRESSING

0000

SU00568

Figure 2. 80C51 Data Memory

8 BYTES

SCRATCH

PAD

AREA

... 7F

BIT

ADDRESSABLE

SEGMENT

0 ...

BANKS

SU00569

Figure 3. 128 Bytes of RAM Direct and Indirect Addressable

1997 Sept 18

Philips Semiconductors

80C51 Family

80C51 family programmer’s guide

and instruction set

Table 1. 80C51 Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

MSB

LSB

RESET VALUE

ACC*

Accumulator

E0H

00H

B register

F0H

00H

DPTR

Data pointer (2 by-

tes)

DPH

Data pointer high

83H

00H

DPL

Data pointer low

82H

00H

IE*

Interrupt enable

A8H

–

ET1

EX1

ET0

EX0

0x000000B

IP*

Interrupt priority

B8H

–

PT1

PX1

PT0

PX0

xx000000B

P0*

Port 0

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

FFH

P1*

Port 1

90H

–

T2EX

FFH

P2*

Port 2

A0H

A15

A14

A13

A12

A11

A10

FFH

P3*

Port 3

B0H

INT1

INT0

TxD

Rxd

FFH

PCON 1

Power control

87H

SMOD

–

GF1

GF0

IDL

0xxxxxxxB

PSW*

Program status word

D0H

RS1

RS0

–

00H

SBUF

Serial data buffer

99H

xxxxxxxxB

SCON*

Serial controller

98H

SM0

SM1

SM2

REN

TB8

RB8

00H

Stack pointer

81H

07H

TCON*

Timer control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TH0

Timer high 0

8CH

00H

TH1

Timer high 1

8DH

00H

TL0

Timer low 0

8AH

00H

TL1

Timer low 1

8BH

00H

TMOD

Timer mode

89H

GATE

C/T

GATE

C/T

00H

NOTES:

* Bit addressable

1. Bits GF1, GF0, PD, and IDL of the PCON register are not implemented on the NMOS 8051/8031.

1997 Sept 18

Philips Semiconductors

80C51 Family

80C51 family programmer’s guide

and instruction set

8 BYTES

ACC

PSW

SCON

SBUF

TCON

TMOD

TL0

TL1

TH0

TH1

DPL

DPH

PCON

BIT ADDRESSABLE

SU00570

Figure 4. SFR Memory Map

1997 Sept 18

Philips Semiconductors

80C51 Family

80C51 family programmer’s guide

and instruction set

Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit is

provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.

RS1

RS0

–

PSW.7

Carry Flag.

PSW.6

Auxiliary Carry Flag.

PSW.5

Flag 0 available to the user for general purpose.

RS1

PSW.4

RS0

PSW.3

PSW.2

Overflow Flag.

–

PSW.1

Usable as a general purpose flag.

PSW.0

Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of ‘1’ bus in

the accumulator.

NOTE:

1. The value presented by RS0 and RS1 selects the corresponding register bank.

RS1

RS0

ADDRESS

00H-07H

08H-0FH

10H-17H

18H-1FH

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.

SMOD

–

GF1

GF0

IDL

SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the Serial

Port is used in modes 1, 2, or 3.

–

Not implemented, reserved for future use.*

–

Not implemented reserved for future use.*

–

Not implemented reserved for future use.*

GF1

General purpose flag bit.

GF0

General purpose flag bit.

Power Down Bit. Setting this bit activates Power Down operation in the 80C51. (Available only in CMOS.)

IDL

Idle mode bit. Setting this bit activates Idle Mode operation in the 80C51. (Available only in CMOS.)

If 1s are written to PD and IDL at the same time, PD takes precedence.

* User software should not write 1s to reserved bits. These bits may be used in future 8051 products to invoke new features.

1997 Sept 18

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