AT45DB011.PDF

Features

• Single 2.7V - 3.6V Supply

• Serial Interface Architecture

• Page Program Operation

– Single Cycle Reprogram (Erase and Program)

– 512 Pages (264 Bytes/Page) Main Memory

• Optional Page and Block Erase Operations

• One 264-byte SRAM Data Buffer

• Internal Program and Control Timer

• Fast Page Program Time – 7 ms Typical

• 120 µs Typical Page to Buffer Transfer Time

• Low Power Dissipation

– 4 mA Active Read Current Typical

– 2 µA CMOS Standby Current Typical

• 13 MHz Max Clock Frequency

• Hardware Data Protection Feature

• Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

1-megabit

2.7-volt Only

Serial

DataFlash ®

Description

The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for

in-system reprogramming. Its 1,081,344 bits of memory are organized as 512 pages

of 264 bytes each. In addition to the main memory, the AT45DB011 also contains one

SRAM data buffer of 264 bytes. Unlike conventional Flash memories that are

accessed randomly with multiple address lines and a parallel interface, the DataFlash

AT45DB011

Recommend using

AT45DB011B for new

designs.

(continued)

Pin Configurations

SOIC

Pin Name

Function

Chip Select

SCK

RESET

GND

VCC

SCK

Serial Clock

Serial Input

Serial Output

AT45DB011

Preliminary 16-

Megabit 2.7-volt

Only Serial

DataFlash

Hardware Page

Write Protect Pin

RESET

Chip Reset

RDY/BUSY

Ready/Busy

PLCC

TSSOP Top View

Type 1

RD Y/BUSY

RE SET

VCC

GND

SCK

RESET

RDY/BUSY

Rev. 1103E–01/01

Note: PLCC package pins 16 and

17 are DON’T CONNECT

uses a serial interface to sequentially access its data. The

simple serial interface facilitates hardware layout,

increases system reliability, minimizes switching noise, and

reduces package size and active pin count. The device is

optimized for use in many commercial and industrial appli-

cations where high density, low pin count, low voltage, and

low power are essential. Typical applications for the

DataFlash are digital voice storage, image storage, and

data storage. The device operates at clock frequencies up

to 13 MHz with a typical active read current consumption of

4mA.

To allow for simple in-system reprogrammability, the

AT45DB011 does not require high input voltages for pro-

gramming. The device operates from a single power

supply, 2.7V to 3.6V, for both the program and read opera-

tions . T he AT45DB011 is enabled through the chip select

pin (CS) and accessed via a three-wire interface consisting

of the Serial Input (SI), Serial Output (SO), and the Serial

Clock (SCK).

All programming cycles are self-timed, and no separate

erase cycle is required before programming.

Block Diagram

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER (264 BYTES)

SCK

RESET

VCC

GND

RDY/BUSY

I/O INTERFACE

Memory Array

To provide optimal flexibility, the memory array of the

AT45DB011 is divided into three levels of granularity com-

prising of sectors, blocks, and pages. The Memory

Architecture Diagram illustrates the breakdown of each

level and details the number of pages per sector and block.

All program operations to the DataFlash occur on a page

by page basis; however, the optional erase operations can

be performed at the block or page level.

AT45DB011

AT45DB011

Memory Architecture Diagram

SECTOR ARCHITECTURE

BLOCK ARCHITECTURE

PAGE ARCHITECTURE

SECTOR 0 = 2112 BYTES (2K + 64)

SECTOR 0

BLOCK 0

BLOCK 1

BLOCK 2

8 Pages

PAGE 0

PAGE 1

BLOCK 3

SECTOR 1 = 65,472 BYTES (62K + 1984)

PAGE 6

PAGE 7

PAGE 8

PAGE 9

BLOCK 29

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

BLOCK 34

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

SECTOR 2 = 67,584 BYTES (64K + 2K)

BLOCK 61

PAGE 509

BLOCK 62

BLOCK 63

PAGE 510

PAGE 511

Block = 2112 bytes

(2K + 64)

Page = 264 bytes

(256 + 8)

Device Operation

The device operation is controlled by instructions from the

host processor. The list of instructions and their associated

opcodes are contained in Tables 1 a nd 2 . A valid instruc-

tion starts with the falling edge of CS followed by the

appropriate 8-bit opcode and the d esi red buffer or main

memory address location. While the CS pin is low, toggling

the SCK pin controls the loading of the opcode and the

desired buffer or main memory address location through

the SI (serial input) pin. All instructions, addresses, and

data are transferred with the most significant bit (MSB) first.

bits (BA8-BA0) specify the starting byte address within the

page. The 32 don’t care bits which follow the 24 address

bits are sent to initialize the read operation. Following the

32 don’t care bits, additional pulses on SCK result i n se rial

data being output on the SO (serial output) pin. The CS pin

must remain low during the loading of the opcode, the

address bits, and the reading of data. When the end of a

page in main memory is reached during a main memory

page read, the device will continue reading at the be ginn ing

of the same page. A low-to-high transition on the CS pin

will terminate the read operation and tri-state the SO pin.

BUFFER READ: Data can be read from the data buffer

using an opcode of 54H. To perform a buffer read, the eight

bits of the opcode must be followed by 15 don’t care bits,

nine address bits, and eight don’t care bits. Since the buffer

size is 264-bytes, nine address bits (BFA8-BFA0) are

required to s pe cify the first byte of data to be read from the

buffer. The CS pin must remain low during the loading of

the opcode, the address bits, the don’t care bits, and the

reading of data. When the end of the buffer is reached, the

device will continue reading back at the beginning of the

buffer. A low-to-high transition on the CS pin will terminate

the read operation and tri-state the SO pin.

Read

By specifying the appropriate opcode, data can be read

from the main memory or from the data buffer.

MAIN MEMORY PAGE READ: A main memory read allows

the user to read data directly from any one of the 512

pages in the main memory, bypassing the data buffer and

leaving the contents of the buffer unchanged. To start a

page read, the 8-bit opcode, 52H, is followed by 24

address bits and 32 don’t care bits. In the AT45DB011, the

first six address bits are reserved for larger density devices

(see Notes on page 9), the next nine address bits (PA8-

PA0) specify the page address, and the next nine address

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page

of data can be transferred from the main memory to buffer.

An 8-bit opcode of 53H is followed by the six reserved bits,

nine address bits (PA8-PA0) which specify the page in

main me mor y that is to be transferred, and nine don’t care

bits. The CS pin must be low while toggling the SCK pin to

load the opcode, the address bits, and the don’t care bits

from the SI pin. The transfer of the page of d ata from the

main memory to the buffer will begin when the CS pin tran-

sitions from a low to a high state. During the transfer of a

page of data (t XFR ), the status register can be read to deter-

mine whether the transfer has been completed or not.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page

of data in main memory can be compared to the data in the

buffer. An 8-bit opcode of 60H is followed by 24 address

bits consisting of the six reserved bits, nine address bits

(PA8-PA0) which specify the page in the main memory that

is to be compared to the buffer, and nine don’t care bits.

The loading of the opcode an d th e address bits is the same

as described previously. The CS pin must be low while tog-

gling the SCK pin to load the opcode, the address bits, and

the don’t car e bit s from the SI pin. On the low-to-high tran-

sition of the CS pin, the 264 bytes in the selected main

memory page will be compared with the 264 bytes in the

buffer. During this time (t XFR ), the status register will indi-

cate that the part is busy. On completion of the compare

operation, bit 6 of the status register is updated with the

result of the compare.

the data stored in the buffer into the specified page in the

main memory. Both the erase and the programming of the

page are internally self-timed and should take place in a

maximum time of t EP . During this time, the status register

will indicate that the part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-

OUT BUILT-IN ERASE: A previously erased page within

main memory can be programmed with the contents of the

buffer. An 8-bit opcode of 88H is followed by the six

reserved bits, nine address bits (PA8-PA0) that specify the

page in the main memory to be written, and nine additional

don ’t care bits. When a low-to-high transition occurs on the

CS pin, the part will program the data stored in the buffer

into the specified page in the main memory. It is necessary

that the page in main memory that is being programmed

has been previously erased. The programming of the page

is internally self-timed and should take place in a maximum

time of t P . During this time, the status register will indicate

that the part is busy.

PAGE ERASE: The optional Page Erase command can be

used to individually erase any page in the main memory

array allowing the Buffer to Main Memory Page Program

without Built-in Erase command to be utilized at a later

time. To perform a Page Erase, an opcode of 81H must be

loaded into the device, followed by six reserved bits, nine

address bits (PA8-PA0), and nine don’t care bits. The nine

address bits are used to specify which page of the memory

array is to be erased. When a low-to-high transition occurs

on the CS pin, the part will erase the selected page to 1s.

The erase operation is internally self-timed and should take

place in a maximum time of t PE . During this time, the status

BLOCK ERASE: A block of eight pages can be erased at

one time allowing the Buffer to Main Memory Page Pro-

gram without Built-in Erase command to be utilized to

reduce programming times when writing large amounts of

data to the device. To perform a Block Erase, an opcode of

50H must be loaded into the device, followed by six

reserved bits, six address bits (PA8-PA3), and 12 don’t

care bits. The six address bits are used to specify which

block of eight pages is to be erased. When a low-to-high

transition occurs on the CS pin, the part will erase the

selected block of eight pages to 1s. The erase operation is

internally self-timed and should take place in a maximum

time of t BE . During this time, the status register will indicate

that the part is busy.

Program

BUFFER WRITE: Data can be shifted in from the SI pin

into the data buffer. To load data into the buffer, an 8-bit

opcode of 84H is followed by 15 don’t care bits and nine

address bits (BFA8-BFA0). The nine address bits specify

the first byte in the buffer to be written. The data is entered

following the address bits. If the end of the data buffer is

reached, the device will wrap around back to the beginning

of the buffer. Data will continue to be loaded in to t he buffer

until a low-to-high transition is detected on the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH

BUILT-IN ERASE: Data written into the buffer can be pro-

grammed into the main memory. An 8-bit opcode of 83H is

followed by the six reserved bits, nine address bits (PA8-

PA0) that specify the page in the main memory to be writ-

ten, and nine additional don ’t care bits. When a low-to-high

transition occurs on the CS pin, the part will first erase the

selected page in main memory to all 1s and then program

AT45DB011

AT45DB011

Block Erase Addressing

PA 8

PA 7

PA 6

PA 5

PA 4

PA 3

PA 2

PA 1

PA 0

B l o c k

•

MAIN MEMORY PAGE PROGRAM: This operation is a

combination of the Buffer Write and Buffer to Main Memory

Page Program with Built-in Erase operations. Data is first

shifted into the buffer from the SI pin and then programmed

into a specified page in the main memory. An 8-bit opcode

of 82H is followed by the six reserved bits and 18 address

bits. The nine most significant address bits (PA8-PA0)

select the page in the main memory where data is to be

written, and the next nine address bits (BFA8-BFA0) select

the first byte in the buffer to be written. After all address bits

are shifted in, the part will take data from the SI pin and

store it in the data buffer. If the end of the buffer is reached,

the device will wrap around back to the beginnin g of the

buffer. When there is a low-to-high transition on the CS pin,

the part will first erase the selected page in main memory to

all 1s and then program the data stored in the buffer into

the specified page in the main memory. Both the erase and

the programming of the page are internally self timed and

should take place in a maximum of time t EP . During this

time, the status register will indicate that the part is busy.

AUTO PAGE REWRITE: This mode is only needed if multi-

ple bytes within a page or multiple pages of data are

modified in a random fashion. This mode is a combination

of two operations: Main Memory Page to Buffer Transfer

and Buffer to Main Memory Page Program with Built-in

Erase. A page of data is first transferred from the main

memory to the data buffer, and then the same data (from

the buffer) is programmed back into its original page of

main memory. An 8-bit opcode of 58H is followed by the six

reserved bits, nine address bits (PA8-PA0) that specify the

page in main memory to be rewritten, and nine additional

don ’t care bits. When a low-to-high transition occurs on the

CS pin, the part will first transfer data from the page in main

memory to the buffer and then program the data from the

buffer back into same page of main memory. The operation

is internally self-timed and should take place in a maximum

time of t EP . During this time, the status register will indicate

that the part is busy.

If a sector is programmed or reprogrammed sequentially

page by page, then the programming algorithm shown in

Figure 1 on page 16 is recommended. Otherwise, if multi-

ple bytes in a page or several pages are programmed

randomly in a sector, then the programming algorithm

shown in Figure 2 on page 17 is recommended.

STATUS REGISTER: The status register can be used to

determine the device’s ready/busy status, the result of a

Main Memory Page to Buffer Compare operation, or the

device density. To read the status register, an opcode of

57H must be loaded into the device. After the last bit of the

opcode is shifted in, the eight bits of the status register,

starting with the MSB (bit 7), will be shifted out on the SO

pin during the next eight clock cycles. The five most signifi-

cant bits of the status register will contain device

information, while the remaining three least significant bits

are reserved for future use and will have undefined values.

After bit 0 of the status register has been shifted out, the

sequence will repeat itself (as long as CS remains low and

SCK is being toggled) starting again with bit 7. The data in

the status register is constantly updated, so each repeating

sequence will output new data.

Ready/Busy status is indicated using bit 7 of the status reg-

ister. If bit 7 is a 1, then the device is not busy and is ready

to accept the next command. If bit 7 is a 0, then the device

is in a busy state. The user can continuously poll bit 7 of the

status register by stopping SCK once bit 7 has been output.

The status of bit 7 will continue to be output on the SO pin,

and once the device is no longer busy, the state of SO will

change from 0 to 1. There are eight operations which can

cause the device to be in a busy state: Main Memory Page

to Buffer Transfer, Main Memory Page to Buffer Compare,

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