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SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
M54/74HC160/161
M54/74HC162/163
. HIGH SPEED
f MAX = 63 MHz (TYP.) AT V CC =5V
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
I CC =4
m
A (MAX.) AT 25
C
. BALANCED PROPAGATION DELAYS
. HIGH NOISE IMMUNITY
V NIH =V NIL =28%V CC (MIN.)
t PLH =t PHL
B1R
(Plastic Package)
F1R
(Ceramic Package)
. WIDE OPERATING VOLTAGE RANGE
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS160
V CC (OPR) = 2 V TO 6 V
~
163
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
DESCRIPTION
M74HCXXXB1R
M74HCXXXC1R
M54/74HC160 Decade, Asynchronous Clear
M54/74HC161 Binary, Asynchronous Clear
M54/74HC162 Decade, Synchronous Clear
M54/74HC163 Binary, Synchronous Clear
The M54/74HC160, 161, 162 and 163 are high
speed CMOS SYNCHRONOUS PRESETTABLE
COUNTERS fabricated with silicon gate C 2 MOS
technology.
They have the same the high speed operation simi-
lar to equivalent LSTTL while maintaining the
CMOS low power dissipation.
The M54/74HC160/162 are BCD Decade counters
and the M54/74HC161/163 are 4 bit binary counter-
s.
The CLOCK input is active on the rising edge. Both
LOAD and CLEAR inputs are active Low.
Presetting of all four IC’s is synchronous on the ris-
ing edge of the CLOCK.
The function on the M54/74HC162/163 is syn-
chronous to CLOCK, while the M54/74HC160/161
counters are cleared asynchronously.
Two enable inputs (TE and PE) and CARRY output
are provided to enable easy cascading of counters,
which facilities easy implementation of N-bit
counters without using external gates.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
PIN CONNECTIONS (top view)
NC =
No Inter-
nal Con-
April 1993
1/16
. LOW POWER DISSIPATION
°
337930529.002.png
M54/M74HC160/161/162/163
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
Asynchronous Master
reset
2
CLOCK
Clock Input (LOW to
HIGH, Edge-triggered)
3, 4, 5, 6
A, B, C, D Data Inputs
7
ENABLE P Count Enable Input
10
ENABLET Count Enable Carry Input
9
LOAD
Parallel Enable Input
14, 13, 12,
11
QA to QD Flip Flop Outputs
15
CARRY
OUTPUT
Terminal Count Output
8
GND
Ground (0V)
16
V CC
Positive Supply Voltage
IEC LOGIC SYMBOL (HC160)
IEC LOGIC SYMBOL (HC161)
IEC LOGIC SYMBOL (HC162)
IEC LOGIC SYMBOL (HC163)
2/16
337930529.003.png
M54/M74HC160/161/162/163
TRUTH TABLE
M54/74HC160/161
M54/74HC162/163
OUTPUTS
INPUTS
INPUTS
FUNCTION
CLR LD
PE
TE
CK CLR LD
PE
TE
CK QA QB QC QD
L
XXXXL
XXX
L
L
L
L
RESET TO ”0”
H
L
X
X
H
L
X
X
A
B
C
D
PRESET DATA
H
H
X
L
H
H
X
L
NO CHANGE
NO COUNT
H
H
L
X
H
H
L
X
NO CHANGE
NO COUNT
HHHH
HHHH
COUNT UP
COUNT
H
X
X
X
X
X
X
X
NO CHANGE
NO COUNT
Note: X : Don’t Care
A, B, C, D : Logi level of data inputs
Carry
: CARRY = TE • Q A • Q B • Q C • Q D ............ (M54/74HC160/162)
: CARRY = TE
•
Q A
•
Q B
•
Q C
•
Q D ............ (M54/74HC161/163)
TIMING CHART (HC160/162 : decade counter)
3/16
337930529.004.png
M54/M74HC160/161/162/163
TIMING CHART (HC161/163 : binary counter)
4/16
337930529.005.png
M54/M74HC160/161/162/163
LOGIC DIAGRAM
HC160
LOGIC DIAGRAM
HC161
5/16
337930529.001.png

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