cd4066.pdf

November 1983

Revised August 2000

CD4066BC

Quad Bilateral Switch

General Description

The CD4066BC is a quad bilateral switch intended for the

transmission or multiplexing of analog or digital signals. It is

pin-for-pin compatible with CD4016BC, but has a much

lower “ON” resistance, and “ON” resistance is relatively

constant over the input-signal range.

High degree linearity 0.1% distortion (typ.)

High degree linearity @ f is =

1 kHz, V is = 5V p-p ,

High degree linearity V DD −

V SS =

10V, R L = 10 k Ω

Extremely low “OFF” 0.1 nA (typ.)

switch leakage: @ V DD −

V SS =

10V, T A =

25 ° C

Features

Extremely high control input impedance 10 12

(typ.)

50 dB (typ.)

between switches @ f is =

Wide supply voltage range 3V to 15V

0.9 MHz, R L =

1 k Ω

High noise immunity 0.45 V DD (typ.)

Frequency response, switch “ON” 40 MHz (typ.)

Wide range of digital and

7.5 V PEAK

Applications

• Analog signal switching/multiplexing

• Signal gating

• Squelch control

• Chopper

• Modulator/Demodulator

• Commutating switch

• Digital signal switching/multiplexing

• CMOS logic implementation

• Analog-to-digital/digital-to-analog conversion

• Digital control of frequency, impedance, phase, and

analog-signal-gain

analog switching

“ON” resistance for 15V operation 80

Matched “ON” resistance

R ON =

5 Ω

(typ.)

over 15V signal input

“ON” resistance flat over peak-to-peak signal range

High “ON”/“OFF” 65 dB (typ.)

output voltage ratio @ f is

10 kHz, R L

10 k

Ordering Code:

Order Number Package Number

Package Description

CD4066BCM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

CD4066BCSJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4066BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Schematic Diagram

DS005665

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Low crosstalk

Absolute Maximum Ratings

(Note 1)

(Note 2)

Recommended Operating

Conditions (Note 2)

Supply Voltage (V DD )

3V to 15V

Supply Voltage (V DD )

−

0.5V to +

18V

Input Voltage (V IN )

0V to V DD

Input Voltage (V IN )

−

0.5V to V CC +

0.5V

Operating Temperature Range (T A )

C to

Storage Temperature Range (T S )

−

65 °

C to +

150 ° C

Power Dissipation (P D )

Dual-In-Line

700 mW

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provide con-

ditions for actual device operation.

Note 2: V SS

Small Outline

500 mW

Lead Temperature (T L )

(Soldering, 10 seconds)

300 ° C

0V unless otherwise specified.

DC Electrical Characteristics (Note 2)

−

40 °

25 °

85 °

Symbol

Parameter

Conditions

Units

Min

Max

Min

Typ

Max

Min

Max

I DD

Quiescent Device Current

V DD =

1.0

0.01

1.0

7.5

V DD =

10V

2.0

0.01

2.0

V DD =

15V

4.0

0.01

4.0

SIGNAL INPUTS AND OUTPUTS

R ON

“ON” Resistance

R L =

10 k Ω

to (V DD −

V SS /2)

V C =

V DD , V SS to V DD

V DD =

850

270

1050

1200

V DD =

10V

330

120

400

520

V DD =

15V

210

240

300

∆ R ON

∆ “ON” Resistance Between

R L =

10 k Ω

to (V DD −

V SS /2)

Any 2 of 4 Switches

V CC =

V DD , V IS =

V SS to V DD

V DD =

10V

V DD =

15V

I IS

Input or Output Leakage

V C =

0.1

200

Switch “OFF”

CONTROL INPUTS

V ILC

LOW Level Input

V IS =

V SS and V DD

Voltage

V OS =

V DD and V SS

I IS =

10 µ

V DD =

1.5

2.25

1.5

V DD =

10V

3.0

4.5

3.0

V DD =

15V

4.0

6.75

4.0

V IHC

HIGH Level Input

V DD =

3.5

2.75

3.5

Voltage

V DD =

10V (Note 7)

7.0

5.5

7.0

V DD =

15V

11.0

8.25

11.0

I IN

Input Current

V DD −

V SS =

15V

0.3

10 − 5

0.3

1.0

V DD ≥

V IS ≥

V SS

V DD ≥

V C ≥

V SS

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AC Electrical Characteristics (Note 3)

T A = 25 °

C, t r =

t f =

20 ns and V SS =

0V unless otherwise noted

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t PHL , t PLH Propagation Delay Time Signal

V C

V DD , C L

50 pF, (Figure 1)

Input to Signal Output

R L

200k

V DD

10V

V DD

15V

t PZH , t PZL Propagation Delay Time

R L

1.0 k

, C L

50 pF, (Figure 2, Figure 3)

Control Input to Signal

V DD

125

Output High Impedance to

V DD

10V

Logical Level

V DD

15V

t PHZ , t PLZ Propagation Delay Time

R L

1.0 k

, C L

50 pF, (Figure 2, Figure 3)

Control Input to Signal

V DD

125

Output Logical Level to

V DD

10V

High Impedance

V DD

15V

Sine Wave Distortion

V C

V DD

5V, V SS

0.1

R L

10 k

, V IS

5V p-p , f

1 kHz, (Figure 4)

Frequency Response-Switch

V C

V DD

5V, V SS

5V,

MHz

“ON” (Frequency at

3 dB)

5V p-p ,

20 Log 10 V OS /V OS (1 kHz)

1 k

, V IS

dB,

(Figure 4)

Feedthrough — Switch “OFF”

V DD

5.0V, V CC

V SS

5.0V,

1.25

(Frequency at

50 dB)

R L

1 k

, V IS

5.0V p-p , 20 Log 10 ,

V OS /V IS

50 dB, (Figure 4)

Crosstalk Between Any Two

V DD

V C(A)

5.0V; V SS

V C(B)

5.0V,

0.9

MHz

Switches (Frequency at

50 dB)

R L 1 k

, V IS(A)

5.0 V p-p , 20 Log 10 ,

V OS(B) /V IS(A)

50 dB (Figure 5)

Crosstalk; Control Input to

V DD

10V, R L

10 k

, R IN

1.0 k

150

mV p-p

Signal Output

V CC

10V Square Wave, C L

50 pF

(Figure 6)

Maximum Control Input

R L

1.0 k

, C L

50 pF, (Figure 7)

V OS(f)

½ V OS (1.0 kHz)

V DD

5.0V

6.0

MHz

V DD

10V

8.0

MHz

V DD

15V

8.5

MHz

C IS

Signal Input Capacitance

8.0

C OS

Signal Output Capacitance

V DD

10V

8.0

C IOS

Feedthrough Capacitance

V C

0.5

C IN

Control Input Capacitance

5.0

7.5

Note 3: AC Parameters are guaranteed by DC correlated testing.

Note 4: These devices should not be connected to circuits with the power “ON”.

Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in C L wherever it is

specified.

Note 6: V IS is the voltage at the in/out pin and V OS is the voltage at the out/in pin. V C is the voltage at the control input.

Note 7: Conditions for V IHC : a) V IS

V DD , I OS

standard B series I OH

b) V IS

0V, I OL

standard B series I OL .

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R L

Typical Performance Characteristics

“ON” Resistance vs Signal

Voltage for T A =

25 °

“ON” Resistance as a Function

of Temperature for

V DD −

V SS

15V

“ON” Resistance as a Function

of Temperature for

V DD −

V SS

10V

“ON” Resistance as a Function

of Temperature for

V DD −

Special Considerations

In applications where separate power sources are used to

drive V DD and the signal input, the V DD current capability

should exceed V DD /R L (R L = effective external load of the 4

CD4066BC bilateral switches). This provision avoids any

permanent current flow or clamp action of the V DD supply

when power is applied or removed from CD4066BC.

In certain applications, the external load-resistor current

may include both V DD and signal-line components. To

avoid drawing V DD current when switch current flows into

terminals 1, 4, 8 or 11, the voltage drop across the bidirec-

tional switch must not exceed 0.6V at T A ≤

25 °

C, or 0.4V at

C (calculated from R ON values shown).

No V DD current will flow through R L if the switch current

flows into terminals 2, 3, 9 or 10.

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V SS

T A

AC Test Circuits and Switching Time Waveforms

FIGURE 1. t PHL , t PLH Propagation Delay Time Signal Input to Signal Output

FIGURE 2. t PZH , t PHZ Propagation Delay Time Control to Signal Output

FIGURE 3. t PZL , t PLZ Propagation Delay Time Control to Signal Output

V C

V DD for distortion and frequency response tests

V C

V SS for feedthrough test

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough

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