cd4069.pdf

SEMICONDUCTOR TECHNICAL DATA

The MC14069UB hex inverter is constructed with MOS P–channel and

N–channel enhancement mode devices in a single monolithic structure.

These inverters find primary use where low power dissipation and/or high

noise immunity is desired. Each of the six inverters is a single stage to

minimize propagation delays.

•

L SUFFIX

CERAMIC

CASE 632

Supply Voltage Range = 3.0 Vdc to 18 Vdc

•

Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

P SUFFIX

PLASTIC

CASE 646

•

Triple Diode Protection on All Inputs (see Page 5–2)

•

Pin–for–Pin Replacement for CD4069UB

•

Meets JEDEC UB Specifications

D SUFFIX

SOIC

CASE 751A

MAXIMUM RATINGS* (Voltages Referenced to V SS )

ÎÎÎÎ

Symbol

Parameter

Value

Unit

V DD

DC Supply Voltage

– 0.5 to + 18.0

ORDERING INFORMATION

MC14XXXUBCP Plastic

MC14XXXUBCL Ceramic

MC14XXXUBD SOIC

T A = – 55 ° to 125 ° C for all packages.

V in , V out

Input or Output Voltage (DC or Transient)

– 0.5 to V DD + 0.5

I in , I out

Input or Output Current (DC or Transient),

per Pin

± 10

P D

Power Dissipation, per Package†

500

T stg

Storage Temperature

– 65 to + 150

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

T L

Lead Temperature (8–Second Soldering)

260

PIN ASSIGNMENT

IN 1

V DD

OUT 1

IN 6

IN 2

OUT 6

LOGIC DIAGRAM

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

OUT 2

IN 5

IN 3

OUT 5

V DD

OUT 3

IN 4

V DD = PIN 14

V SS = PIN 7

V SS

OUT 4

INPUT*

OUTPUT

V SS

* Double diode protection on all

inputs not shown.

20 ns

V DD

90%

50%

10%

OUTPUT

PULSE

GENERATOR

INPUT

V SS

V OH

INPUT

t PHL

t PLH

V SS

C L

90%

50%

10%

OUTPUT

V OL

t THL

t TLH

Figure 1. Switching Time Test Circuit and Waveforms

REV 3

1/94

MOTOROLA CMOS LOGIC DATA

MC14069UB

Motorola, Inc. 1995

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )

ÎÎÎÎÎÎÎÎÎÎÎ

V DD

Vdc

– 55 C

25 C

125 C

V DD

Vdc

Characteristic

Symbol

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

“0” Level

V OL

5.0

—

0.05

—

0.05

—

0.05

Vdc

V in = V DD

V in = 0

“1” Level

V OH

5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Input Voltage

“0” Level

V IL

Vdc

(V O = 4.5 Vdc)

(V O = 9.0 Vdc)

(V O = 13.5 Vdc)

5.0

—

1.0

2.0

2.5

—

2.25

4.50

6.75

1.0

2.0

2.5

—

1.0

2.0

2.5

“1” Level

V IH

Vdc

(V O = 0.5 Vdc)

(V O = 1.0 Vdc)

(V O = 1.5 Vdc)

5.0

4.0

8.0

12.5

—

4.0

8.0

12.5

2.75

5.50

8.25

—

4.0

8.0

12.5

—

Output Drive Current

(V OH = 2.5 Vdc)

I OH

mAdc

Source

5.0

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

(V OH = 4.6 Vdc)

(V OH = 9.5 Vdc)

(V OH = 13.5 Vdc)

(V OL = 0.4 Vdc)

Sink

I OL

5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

(V OL = 0.5 Vdc)

(V OL = 1.5 Vdc)

Input Current

I in

—

± 0.1

—

± 0.00001

± 0.1

—

± 1.0

m Adc

Input Capacitance

(V in = 0)

C in

—

5.0

7.5

—

Quiescent Current

(Per Package)

I DD

5.0

—

0.25

0.5

1.0

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

7.5

Adc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Gate) (C L = 50 pF)

I T

5.0

I T = (0.3 m A/kHz) f + I DD /6

I T = (0.6 m A/kHz) f + I DD /6

I T = (0.9 m A/kHz) f + I DD /6

m Adc

Output Rise and Fall Times**

(C L = 50 pF)

t TLH , t THL = (1.35 ns/pF) C L + 33 ns

t TLH , t THL = (0.60 ns/pF) C L + 20 ns

t TLH , t THL = (0.40 ns/pF) C L + 20 ns

t TLH ,

t THL

5.0

—

100

200

100

—

Propagation Delay Times**

(C L = 50 pF)

t PLH , t PHL = (0.90 ns/pF) C L + 20 ns

t PLH , t PHL = (0.36 ns/pF) C L + 22 ns

t PLH , t PHL = (0.26 ns/pF) C L + 17 ns

t PLH ,

t PHL

5.0

—

125

—

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** The formulas given are for the typical characteristics only at 25 C.

†To calculate total supply current at loads other than 50 pF:

I T (C L ) = I T (50 pF) + (C L – 50) Vfk

where: I T is in m A (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, V in and V out should be constrained to the range V SS

(V in or V out )

MC14069UB

MOTOROLA CMOS LOGIC DATA

Characteristic

ÎÎÎ

Symbol

Unit

V DD .

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must

be left open.

OUTLINE DIMENSIONS

–A–

L SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–B–

INCHES

MILLIMETERS

DIM MIN

MAX

MIN

MAX

0.750 0.785 19.05 19.94

0.245 0.280

6.23

7.11

–T–

SEATING

PLANE

0.155 0.200

3.94

5.08

0.015 0.020

0.39

0.50

0.055 0.065

1.40

1.65

0.100 BSC

2.54 BSC

0.008 0.015

0.21

0.38

0.125 0.170

3.18

4.31

14 PL

0.300 BSC

7.62 BSC

0.25 (0.010)

1.01

0.020 0.040

0.51

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

INCHES

MILLIMETERS

DIM MIN

MAX

MIN

MAX

0.715 0.770 18.16 19.56

0.240 0.260

6.10

6.60

0.145 0.185

3.69

4.69

0.015 0.021

0.38

0.53

0.040 0.070

1.02

1.78

0.100 BSC

2.54 BSC

0.052 0.095

1.32

2.41

0.008 0.015

0.20

0.38

0.115 0.135

2.92

3.43

SEATING

PLANE

0.300 BSC

7.62 BSC

0.015 0.039

0.39

1.01

MOTOROLA CMOS LOGIC DATA

MC14069UB

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A –

–B–

P 7 PL

0.25 (0.010)

B M

MILLIMETERS

INCHES

R X 45

DIM MIN

MAX

MIN

MAX

8.55

8.75 0.337 0.344

3.80

4.00 0.150 0.157

1.35

1.75 0.054 0.068

0.35

0.49 0.014 0.019

–T–

0.40

1.25 0.016 0.049

SEATING

PLANE

D 14 PL

1.27 BSC

0.050 BSC

0.19

0.25 0.008 0.009

0.25 (0.010)

A S

0.10

0.25 0.004 0.009

5.80

6.20 0.228 0.244

0.25

0.50 0.010 0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided

in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,

including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

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into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a

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MC14069UB