max1003.pdf

19-1236; Rev 0; 6/97

Low-Power, 90Msps, Dual 6-Bit ADC

_______________General Description

The MAX1003 is a dual, 6-bit analog-to-digital converter

(ADC) that combines high-speed, low-power operation

with a user-selectable input range, an internal refer-

ence, and a clock oscillator. The dual parallel ADCs are

designed to convert in-phase (I) and quadrature (Q)

analog signals into two 6-bit, offset-binary-coded digital

outputs at sampling rates up to 90Msps. The ability to

directly interface with baseband I and Q signals makes

the MAX1003 ideal for use in direct-broadcast satellite,

VSAT, and QAM16 demodulation applications.

The MAX1003 input amplifiers feature true differential

inputs, a -0.5dB analog bandwidth of 55MHz, and user-

programmable input full-scale ranges of 125mVp-p,

250mVp-p, or 500mVp-p. With an AC-coupled input

signal, matching performance between input channels

is typically better than 0.1dB gain, 1/4LSB offset, and

0.5° phase. Dynamic performance is 5.85 effective

number of bits (ENOB) with a 20MHz analog input sig-

nal, or 5.7 ENOB with a 50MHz signal.

The MAX1003 operates with +5V analog and +3.3V digi-

tal supplies for easy interfacing to +3.3V-logic-compati-

ble digital signal processors and microprocessors. It

comes in a 36-pin SSOP package.

________________________Applications

Direct Broadcast Satellite (DBS) Receivers

VSAT Receivers

Wide Local Area Networks (WLANs)

Cable Television Set-Top Boxes

____________________________Features

Two Matched 6-Bit ADCs

High Sampling Rate: 90Msps per ADC

Low Power Dissipation: 350mW

Excellent Dynamic Performance:

5.85 ENOB with 20MHz Analog Input

5.7 ENOB with 50MHz Analog Input

±1/4LSB INL and DNL (typ)

Internal Bandgap Voltage Reference

Internal Oscillator with Overdrive Capability

55MHz (-0.5dB) Bandwidth Input Amplifiers with

True Differential Inputs

User-Selectable Input Full-Scale Range

(125mVp-p, 250mVp-p, or 500mVp-p)

1/4LSB Channel-to-Channel Offset Matching (typ)

0.1dB Gain and 0.5° Phase Matching (typ)

Single-Ended or Differential Input Drive

Flexible, 3.3V, CMOS-Compatible Digital Outputs

______________Ordering Information

PART

MAX1003CAX

TEMP. RANGE

PIN-PACKAGE

36 SSOP

0°C to +70°C

Pin Configuration appears at end of data sheet.

_________________________________________________________Functional Diagram

IOCC+

IOCC-

IIN+

INPUT

AMP

ADC

DATA

BUFFER

DI0–DI5

IIN-

VREF

OFFSET

CORREC-

TION I

CLOCK

OUT

D C LK

GAIN

BANDGAP

REFERENCE

CLOCK

DRIVER

TNK+

TNK-

OFFSET

CORREC-

TION Q

QIN+

MAX1003

VREF

INPUT

AMP

DATA

BUFFER

DQ0–DQ5

ADC

QIN-

QOCC+

QOCC-

________________________________________________________________ Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

Low-Power, 90Msps, Dual 6-Bit ADC

ABSOLUTE MAXIMUM RATINGS

V CC to GND ............................................................-0.3V to 6.5V

V CCO to OGND ........................................................-0.3V to 6.5V

GND to OGND ........................................................-0.3V to 0.3V

Digital and Clock Output Pins to OGND...-0.3V to V CCO (10sec)

All Other Pins to GND...............................................-0.3V to V CC

Continuous Power Dissipation (T A = +70°C)

SSOP (derate 11.8mW/°C above +70°C) ...................941mW

Operating Temperature Range...............................0°C to +70°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, <10sec)...........................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

(V CC = +5V ±5%, V CCO = 3.3V ±300mV, T A = T MIN to T MAX , unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY (Note 1)

Resolution

RES

Bits

Integral Nonlinearity

INL

-0.5

±0.25

0.5

LSB

Differential Nonlinearity

DNL

No missing codes over temperature

-0.5

±0.25

0.5

LSB

V FSH

GAIN = V CC (high gain)

118.75

125

131.25

Full-Scale Input Range

V FSM

GAIN = open (mid gain)

237.5

250

262.5

mVp-p

V FSL

GAIN = GND (low gain)

475

500

525

INVERTING AND NONINVERTING ANALOG INPUTS

Input Open-Circuit Voltage

V AOC

2.25

2.35

2.45

Input Resistance

R IN

Input Capacitance

C IN

Guaranteed by design

Common-Mode Voltage Range

V CM

Other analog input driven with external source

(Note 2)

1.75

2.75

OSCILLATOR INPUTS

Oscillator Input Resistance

R OSC

Other oscillator input tied to V CC + 0.3V

4.8

12.1

k ½

DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)

Digital Outputs Logic-High

Voltage

V OH

I SOURCE = 50µA

0.7V CCO

Digital Outputs Logic-Low

Voltage

V OL

I SINK = 400µA

0.5

POWER SUPPLY

Supply Current

I CC

104

Power-Supply Rejection Ratio

PSRR

V CC = 4.75V to 5.25V (Note 3)

20MHz, full-scale I and Q analog inputs,

C L = 15pF (Note 4)

-75

-40

Digital Outputs Supply Current

I CCO

Power Dissipation

350

2 _______________________________________________________________________________________

Low-Power, 90Msps, Dual 6-Bit ADC

AC ELECTRICAL CHARACTERISTICS

(V CC = +5V ±5%, V CCO = 3.3V ±300mV, T A = +25°C, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), V INI = V INQ = 20MHz sine, amplitude -1dB below

full scale, unless otherwise noted.)

Maximum Sample Rate

f MAX

Msps

Analog Input -0.5dB Bandwidth

GAIN = GND, open, V CC

MHz

GAIN = open (mid gain)

5.6

5.85

ENOB M

GAIN = open (mid gain), f IN = 50MHz,

-1dB below full scale

5.7

Effective Number of Bits

Bits

ENOB H

GAIN = V CC (high gain)

5.8

ENOB L

GAIN = GND (low gain)

5.85

Signal-to-Noise plus Distortion

Ratio

SINAD

GAIN = open (mid gain)

35.5

Input Offset (Note 5)

OFF

I channel

-0.5

0.5

LSB

Q channel

-0.5

0.5

Crosstalk Between ADCs

XTLK

-55

Offset Mismatch Between ADCs

OMM

(Note 5)

-0.5

±0.25

0.5

LSB

Amplitude Match Between

ADCs

-0.2

±0.1

0.2

Phase Match Between ADCs

-2

±0.5

degrees

TIMING CHARACTERISTICS (Data outputs: R L = 1M

, C L = 15pF)

Clock to Data Propagation

Delay

t PD

(Note 6)

3.6

Data Valid Skew

t SKEW

(Note 6)

1.5

Input to DCLK Delay

t DCLK

TNK+ to DCLK (Note 6)

5.3

Aperture Delay

t AD

Figure 8

7.5

Pipeline Delay

Figure 8

clock

cycle

Note 1: Best-fit straight-line linearity method.

Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).

However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-

mode input range (Figures 4 and 5).

Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in V CC supply voltage,

expressed in decibels.

Note 4: The current in the V CCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-

sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-

ital outputs to a minimum.

Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).

Note 6: t PD and t SKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a

data bit. t DCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-

itive load on the outputs is 15pF.

_______________________________________________________________________________________ 3

Low-Power, 90Msps, Dual 6-Bit ADC

__________________________________________Typical Operating Characteristics

(V CC = +5V ±5%, V CCO = 3.3V ±300mV, f CLK = 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, T A = +25°C, unless

otherwise noted.)

EFFECTIVE NUMBER OF BITS

vs. ANALOG INPUT FREQUENCY

ANALOG INPUT BANDWIDTH

EFFECTIVE NUMBER OF BITS

vs. SAMPLING/CLOCK FREQUENCY

6.0

5.8

5.9

-0.2

5.6

5.8

-0.4

5.4

-0.6

5.7

5.2

-0.8

5.6

f CLK = 90Msps

f IN = 20MHz

5.0

-1.0

5.5

100

ANALOG INPUT FREQUENCY (MHz)

CLOCK FREQUENCY (MHz)

OSCILLATOR OPEN-LOOP PHASE NOISE

vs. FREQUENCY OFFSET

FFT PLOT

-50

f IN = 19.9512MHz

f CLK = 90.000MHz

1024 POINTS

AC COUPLED

SINGLE ENDED

AVERAGED

-70

-20

-90

-110

-40

-130

-60

10k

100k

FREQUENCY OFFSET FROM CARRIER (Hz)

FREQUENCY (MHz)

INTEGRAL NONLINEARITY

vs. CODE

DIFFERENTIAL NONLINEARITY

vs. CODE

0.50

0.25

-0.25

-0.50

CODE

4 _______________________________________________________________________________________

Low-Power, 90Msps, Dual 6-Bit ADC

______________________________________________________________Pin Description

NAME

FUNCTION

GAIN

Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).

IOCC+

Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled

inputs. Ground for DC-coupled inputs.

IOCC-

Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled

inputs. Ground for DC-coupled inputs.

IIN+

I-Channel Noninverting Analog Input

IIN-

I-Channel Inverting Analog Input

V CC

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).

7, 11, 12,

18, 19

GND

Analog Ground

V CC

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11).

TNK+

Positive Oscillator/Clock Input

TNK-

Negative Oscillator/Clock Input

V CC

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12).

QIN-

Q-Channel Inverting Analog Input

QIN+

Q-Channel Noninverting Analog Input

QOCC-

Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled

inputs. Ground for DC-coupled inputs.

QOCC+

Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled

inputs. Ground for DC-coupled inputs.

20–25

DQ5–DQ0

Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).

26, 28

V CCO

Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).

OGND

Digital Output Ground

DCLK

Digital Clock Output. Frames the output data.

30–35

DI0–DI5

I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).

V CC

+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19).

_______________Detailed Description

Programmable Input Amplifiers

The MAX1003 has two (I and Q) programmable-gain

input amplifiers with a -0.5dB bandwidth of 55MHz and

true differential inputs. To maximize performance in

high-speed systems, each amplifier has less than 5pF

of input capacitance. The input amplifier gain is pro-

grammed, via the GAIN pin, to provide three possible

input full-scale ranges (FSRs) as shown in Table 1.

Converter Operation

The MAX1003 contains two 6-bit analog-to-digital con-

verters (ADCs), a buffered voltage reference, and oscil-

lator circuitry. The ADCs use a flash conversion

technique to convert an analog input signal into a 6-bit

parallel digital output code. The MAX1003’s unique

design includes 63 fully differential comparators and a

proprietary encoding scheme that ensures no more

than 1LSB dynamic encoding error. The control logic

interfaces easily to most digital signal processors

(DSPs) and microprocessors (µPs) with +3.3V CMOS-

compatible logic interfaces. Figure 1 shows the

MAX1003 in a typical application.

Table 1. Input Amplifier Programming

GAIN

INPUT FULL-SCALE RANGE

(mVp-p)

GND

500

Open

250

V CC

125

_______________________________________________________________________________________ 5

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