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INTEGRATED CIRCUITS
NE570/571/SA571
Compandor
Product specification
1990 Jun 7
IC17 Data Handbook
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Philips Semiconductors
Product specification
Compandor
NE570/571/SA571
DESCRIPTION
The NE570/571 is a versatile low cost dual gain control circuit in
which either channel may be used as a dynamic range compressor
or expandor. Each channel has a full-wave rectifier to detect the
average value of the signal, a linerarized temperature-compensated
variable gain cell, and an operational amplifier.
The NE570/571 is well suited for use in cellular radio and radio
communications systems, modems, telephone, and satellite
broadcast/receive audio systems.
PIN CONFIGURATION
D, F, and N Packa g es 1
RECT CAP 1
1
2
3
4
5
6
7
8
16
15
RECT CAP 2
RECT IN 1
AG CELL IN 1
GND
RECT IN 2
14
AG CELL IN 2
13
V CC
INV. IN 1
RES. R 3 1
OUTPUT 1
12
INV. IN 2
RES. R 3 2
OUTPUT 2
FEATURES
•
11
10
Complete compressor and expandor in one IChip
THD TRIM 1
9
THD TRIM 2
•
Temperature compensated
•
Greater than 110dB dynamic range
TOP VIEW
NOTE:
1. SOL - Released in Large SO Package Only.
SR00675
•
Operates down to 6VDC
Figure 1. Pin Configuration
•
System levels adjustable with external components
•
Distortion may be trimmed out
•
Telephone trunk compandor—570
•
Dynamic noise reduction systems
•
Telephone subscriber compandor—571
•
Voltage-controlled amplifier
•
High level limiter
•
Low level expandor—noise gate
APPLICATIONS
•
•
Dynamic filters
Cellular radio
•
CD Player
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
16-Pin Plastic Small Outline Large (SOL)
0 to +70
°
C
NE570D
SOT162-1
16-Pin Ceramic Dual In-Line Package (Cerdip)
0 to +70 ° C
NE570F
0582B
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70
°
C
NE570N
SOT28-4
16-Pin Plastic Small Outline Large (SOL)
0 to +70 ° C
NE571D
SOT162-1
16-Pin Ceramic Dual In-Line Package (Cerdip)
0 to +70
°
C
NE571F
0582B
16-Pin Plastic Dual In-Line Package (DIP)
0 to +70 ° C
NE571N
SOT28-4
16-Pin Plastic Small Outline Large (SOL)
-40 to +85
C
SA571D
SOT162-1
16-Pin Ceramic Dual In-Line Package (Cerdip)
-40 to +85 ° C
SA571F
0582B
16-Pin Plastic Dual In-Line Package (DIP)
-40 to +85
C
SA571N
SOT28-4
BLOCK DIAGRAM
THD TRIM
R3
INVERTER IN
R2 20k
R3 20k
D G IN
VARIABLE
GAIN
–
OUTPUT
V REF
+
R4 30k 1.8V
R1 10k
RECT IN
RECTIFIER
RECT CAP
SR00676
Figure 2. Block Diagram
1990 Jun 7
2
853-0812 99768
°
°
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Philips Semiconductors
Product specification
Compandor
NE570/571/SA571
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
V CC
Maximum operating voltage
570
571
24
18
VDC
T A
Operating ambient temperature range
NE
SA
0 to 70
-40 to +85
° C
P D
Power dissipation
400
mW
AC ELECTRICAL CHARACTERISTICS
V CC = +6V, T A = 25 ° C; unless otherwise s tated.
LIMITS
LIMITS
NE/SA571 5
SYMBOL
PARAMETER
TEST CONDITIONS
NE570
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
V CC
Supply voltage
6
24
6
18
V
I CC
Supply current
No signal
3.2
4.8
3.2
4.8
mA
I OUT
Output current capability
± 20
± 20
mA
SR
Output slew rate
±
.5
±
.5
V/
m
s
Gain cell distortion 2
Untrimmed
Trimmed
0.3
0.05
1.0
0.5
0.1
2.0
%
Resistor tolerance
± 5
± 15
± 5
± 15
%
Internal reference voltage
1.7
1.8
1.9
1.65
1.8
1.95
V
Output DC shift 3
Untrimmed
± 20
± 100
± 30
± 150
mV
Expandor output noise
No signal, 15Hz-20kHz 1
20
45
20
60
m V
Unity gain level 6
1kHz
-1
0
+1
-1.5
0
+1.5
dBm
Gain change 2, 4
± 0.1
± 0.2
± 0.1
dB
Reference drift 4
±
5
±
10
+2, -25 +20, -50
mV
Resistor drift 4
+1, -0
+8, -0
%
Tracking error (measured
relative to value at unity
gain) equals [V O - V O (unity
gain)] dB - V 2 dBm
Rectifier input,
V 2 = +6dBm, V 1 = 0dB
+0.2
+0.2
dB
V 2 = -30dBm, V 1 = 0dB
+0.2
-0.5, +1
+0.2
-1, +1.5
Channel separation
60
60
dB
NOTES:
1. Input to V 1 and V 2 grounded.
2. Measured at 0dBm, 1kHz.
3. Expandor AC input change from no signal to 0dBm.
4. Relative to value at T A = 25
°
°
C temperature range.
6. 0dBm = 775mV RMS .
1990 Jun 7
3
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
C.
5. Electrical characteristics for the SA571 only are specified over -40 to +85
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Philips Semiconductors
Product specification
Compandor
NE570/571/SA571
CIRCUIT DESCRIPTION
The NE570/571 compandor building blocks, as shown in the block
diagram, are a full-wave rectifier, a variable gain cell, an operational
amplifier and a bias system. The arrangement of these blocks in the
IC result in a circuit which can perform well with few external
components, yet can be adapted to many diverse applications.
The full-wave rectifier rectifies the input current which flows from the
rectifier input, to an internal summing node which is biased at V REF .
The rectified current is averaged on an external filter capacitor tied
to the C RECT terminal, and the average value of the input current
controls the gain of the variable gain cell. The gain will thus be
proportional to the average value of the input signal for
capacitively-coupled voltage inputs as shown in the following
equation. Note that for capacitively-coupled inputs there is no offset
voltage capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally) which is
less than 0.1 m A.
bias current for the D G cell. The low tempco of this type of reference
provides very stable biasing over a wide temperature range.
The typical performance characteristics illustration shows the basic
input-output transfer curve for basic compressor or expander
circuits.
+20
+10
0
–10
–20
–30
–40
G
|V IN
V REF
|avg
–50
R 1
or
–60
|V IN |avg
R 1
The speed with which gain changes to follow changes in input signal
levels is determined by the rectifier filter capacitor. A small capacitor
will yield rapid response but will not fully filter low frequency signals.
Any ripple on the gain control signal will modulate the signal passing
through the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so there is a
trade-off to be made between fast attack and decay times and
distortion. For step changes in amplitude, the change in gain with
time is shown by this equation.
G(t)
–70
–80
–40
–30
–20
–10
0
+10
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
SR00677
Figure 3. Basic Input-Output Transfer Curve
TYPICAL TEST CIRCUIT
V CC = 15V
(G initial G final ) e t
0.1
m
F
10
m
F
G final
;
10k x C RECT
13
The variable gain cell is a current-in, current-out device with the ratio
I OUT /I IN controlled by the rectifier. I IN is the current which flows from
the D G input to an internal summing node biased at V REF . The
following equation applies for capacitively-coupled inputs. The
output current, I OUT , is fed to the summing node of the op amp.
6.11
20k
2.2
m
F
20k
D G
V 1
V O
7.10
3.14
V IN
R 2
A compensation scheme built into the D G cell compensates for
temperature and cancels out odd harmonic distortion. The only
distortion which remains is even harmonics, and they exist only
because of internal offset voltages. The THD trim terminal provides
a means for nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally compensated) has the
non-inverting input tied to V REF , and the inverting input connected to
the
V IN
V REF
R 2
I IN
V REF
2 .2
10k
V 2
30k
2.15
4
1.16
5.12
8.9
2.2
8.2k
200pF
G cell output as well as brought out externally. A resistor, R 3 , is
brought out from the summing node and allows compressor or
expander gain to be determined only by internal components.
The output stage is capable of
D
SR00678
Figure 4. Typical Test Circuit
20mA output current. This allows a
+13dBm (3.5V RMS ) output into a 300 W load which, with a series
resistor and proper transformer, can result in +13dBm with a 600 W
output impedance.
A bandgap reference provides the reference voltage for all summing
nodes, a regulated supply voltage for the rectifier and D G cell, and a
±
INTRODUCTION
Much interest has been expressed in high performance electronic
gain control circuits. For non-critical applications, an integrated
circuit operational transconductance amplifier can be used, but
when high-performance is required, one has to resort to complex
discrete circuitry with many expensive, well-matched components.
1990 Jun 7
4
G
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Philips Semiconductors
Product specification
Compandor
NE570/571/SA571
This paper describes an inexpensive integrated circuit, the NE570
Compandor, which offers a pair of high performance gain control
circuits featuring low distortion (<0.1%), high signal-to-noise ratio
(90dB), and wide dynamic range (110dB).
rectifier and D G cell (located at the right of R 1 and R 2 ) have the
same potential. The THD trim pin is also at the V REF potential.
Figure 7 shows how the circuit is hooked up to realize an expandor.
The input signal, V IN , is applied to the inputs of both the rectifier and
the
CIRCUIT BACKGROUND
The NE570 Compandor was originally designed to satisfy the
requirements of the telephone system. When several telephone
channels are multiplexed onto a common line, the resulting
signal-to-noise ratio is poor and companding is used to allow a wider
dynamic range to be passed through the channel. Figure 5
graphically shows what a compandor can do for the signal-to-noise
ratio of a restricted dynamic range channel. The input level range of
+20 to -80dB is shown undergoing a 2-to-1 compression where a
2dB input level change is compressed into a 1dB output level
change by the compressor. The original 100dB of dynamic range is
thus compressed to a 50dB range for transmission through a
restricted dynamic range channel. A complementary expansion on
the receiving end restores the original signal levels and reduces the
channel noise by as much as 45dB.
The significant circuits in a compressor or expander are the rectifier
and the gain control element. The phone system requires a simple
full-wave averaging rectifier with good accuracy, since the rectifier
accuracy determines the (input) output level tracking accuracy. The
gain cell determines the distortion and noise characteristics, and the
phone system specifications here are very loose. These specs could
have been met with a simple operational transconductance
multiplier, or OTA, but the gain of an OTA is proportional to
temperature and this is very undesirable. Therefore, a linearized
transconductance multiplier was designed which is insensitive to
temperature and offers low noise and low distortion performance.
These features make the circuit useful in audio and data systems as
well as in telecommunications systems.
G cell. When the input signal drops by 6dB, the gain control
current will drop by a factor of 2, and so the gain will drop 6dB. The
output level at V OUT will thus drop 12dB, giving us the desired 2-to-1
expansion.
D
Figure 8 shows the hook-up for a compressor. This is essentially an
expandor placed in the feedback loop of the op amp. The D G cell is
setup to provide AC feedback only, so a separate DC feedback loop
is provided by the two R DC and C DC . The values of R DC will
determine the DC bias at the output of the op amp. The output will
bias to:
V OUT
DC
1
R DC1 R DC2
R 4
THD TRIM
8,9
R 3
INV IN
6,11 5,12
R 2
R 3
G IN
3,14
20 k
20k
D G
O UT PUT
7,10
R 4
30k
V RE F
1.8V
IG
REC T IN
2,15
R 1
10k
1,16
C RECT
V CC PIN 13
GND PIN 4
SR00680
Figure 6. Chip Block Diagram (1 of 2 Channels)
R 3
*C IN1
R 2
BASIC CIRCUIT HOOK-UP AND OPERATION
Figure 6 shows the block diagram of one half of the chip, (there are
two identical channels on the IC). The full-wave averaging rectifier
provides a gain control current, I G , for the variable gain ( D G) cell.
The output of the D G cell is a current which is fed to the summing
node of the operational amplifier. Resistors are provided to establish
circuit gain and set the output DC bias.
D
G
–
+
V OUT
V IN
R 4
V REF
*C IN2
R 1
NOTE:
2R 3 V IN
(avg)
*C RECT
GAIN
R 1
R 2
I B
A
*EXTERNAL COMPONENTS
I B = 140
m
INPUT
LEVE L
OUTPUT
LEVEL
SR00681
+20
0dB
–20
0dB
Figure 7. Basic Expander
–40
–40
V REF
1
R DCTOT
30k
1.8V
NOISE
The output of the expander will bias up to:
–80
–80
R 3
R 4
SR00679
V OUT
DC 1
V REF
Figure 5. Restricted Dynamic Range Channel
The circuit is intended for use in single power supply systems, so
the internal summing nodes must be biased at some voltage above
ground. An internal band gap voltage reference provides a very
stable, low noise 1.8V reference denoted V REF . The non-inverting
input of the op amp is tied to V REF , and the summing nodes of the
V REF
1
20k
30k
1.8V
3.0V
The output will bias to 3.0V when the internal resistors are used.
External resistors may be placed in series with R 3 , (which will affect
the gain), or in parallel with R 4 to raise the DC bias to any desired
value.
1990 Jun 7
5
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