BUK9624-55_1.pdf

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Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9624-55
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V DS
Drain-source voltage
55
V
mounting. Using ’ trench ’ technology
I D
Drain current (DC)
45
A
the device features very low on-state
P tot
Total power dissipation
103
W
resistance and has integral zener
T j
Junction temperature
175
˚C
diodes giving ESD protection up to
R DS(ON)
Drain-source on-state
24
m
W
2kV. It is intended for use in
resistance
V GS = 5 V
automotive and general purpose
switching applications.
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
d
mb
1
gate
2
drain
3
source
g
2
mb drain
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DS
Drain-source voltage
-
-
55
V
V DGR
Drain-gate voltage
R GS = 20 k
W
-
55
V
±
V GS
Gate-source voltage
-
-
10
V
I D
Drain current (DC)
T mb = 25 ˚C
-
45
A
I D
Drain current (DC)
T mb = 100 ˚C
-
31
A
I DM
Drain current (pulse peak value)
T mb = 25 ˚C
-
180
A
P tot
Total power dissipation
T mb = 25 ˚C
-
103
W
T stg , T j
Storage & operating temperature
-
- 55
175
˚C
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage, all pins
(100 pF, 1.5 k
W
)
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R th j-mb
Thermal resistance junction to
-
-
1.45
K/W
mounting base
R th j-a
Thermal resistance junction to
Minimum footprint, FR4
50
-
K/W
ambient
board
April 1998
1
Rev 1.000
22888863.003.png 22888863.004.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9624-55
Logic level FET
STATIC CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA;
55
-
-
V
voltage
T j = -55˚C
50
-
-
V
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 1 mA
1
1.5
2
V
T j = 175˚C
0.5
-
-
V
T j = -55˚C
-
-
2.3
I DSS
Zero gate voltage drain current V DS = 55 V; V GS = 0 V;
-
0.05
10
m
A
T j = 175˚C
-
-
500
m
A
I GSS
Gate source leakage current
V GS =
±
5 V; V DS = 0 V
-
0.02
1
m
A
T j = 175˚C
-
10
m
A
±
V (BR)GSS Gate-source breakdown
I G =
±
1 mA;
10
-
-
V
voltage
R DS(ON)
Drain-source on-state
V GS = 5 V; I D = 25 A
-
19
24
m
W
resistance
T j = 175˚C
-
-
50
m
W
DYNAMIC CHARACTERISTICS
T mb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
g fs
Forward transconductance
V DS = 25 V; I D = 25 A
15
40
-
S
C iss
Input capacitance
V GS = 0 V; V DS = 25 V; f = 1 MHz
-
1500 2000
pF
C oss
Output capacitance
-
300
360
pF
C rss
Feedback capacitance
-
150
200
pF
t d on
Turn-on delay time
V DD = 30 V; I D = 25 A;
-
30
45
ns
t r
Turn-on rise time
V GS = 5 V; R G = 10
W
-
80
130
ns
t d off
Turn-off delay time
Resistive load
-
95
135
ns
t f
Turn-off fall time
-
40
55
ns
L d
Internal drain inductance
Measured from upper edge of drain
-
2.5
-
nH
tab to centre of die
L s
Internal source inductance
Measured from source lead
-
7.5
-
nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I DR
Continuous reverse drain
-
-
45
A
current
I DRM
Pulsed reverse drain current
-
-
160
A
V SD
Diode forward voltage
I F = 25 A; V GS = 0 V
-
0.95
1.2
V
I F = 40 A; V GS = 0 V
-
1.0
-
t rr
Reverse recovery time
I F = 40 A; -dI F /dt = 100 A/
m
s;
-
40
-
ns
Q rr
Reverse recovery charge
V GS = -10 V; V R = 30 V
-
0.07
-
m
C
April 1998
2
Rev 1.000
22888863.005.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9624-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
W DSS
Drain-source non-repetitive
I D = 40 A; V DD
£
25 V;
-
-
80
mJ
unclamped inductive turn-off
V GS = 10 V; R GS = 50
W
; T mb = 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID / A
7524-55
RDS(ON) = VDS / ID
100
tp = 10 us
100 us
10
DC
1 ms
10 ms
100 ms
0
20 40 60 80 100 120 140 160 180
Tmb / C
1
1
10
100
1000
VDS / V
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T mb )
Fig.3. Safe operating area. T mb = 25 ˚C
I D & I DM = f(V DS ); I DM single pulse; parameter t p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
10
Transient thermal impedance, Zth (K/W)
1
0.5
0.2
0.1
0.05
0.02
0.1
P
t p
D =
t p
D
T
0.01
0
T
t
0
20 40 60 80 100 120 140 160 180
Tmb / C
0.001
10us
1ms
0.1s
10s
pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100
I D /I D 25 ˚C = f(T mb ); conditions: V GS
³
5 V
Fig.4. Transient thermal impedance.
Z th j-mb = f(t); parameter D = t p /T
April 1998
3
Rev 1.000
×
22888863.006.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9624-55
Logic level FET
100
10
8
6
40
gfs/S
VGS/V =
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
ID/A
35
80
30
60
25
40
20
15
20
10
0
5
0
2
4
VSD/V
6
8
10
0
20
40
ID/A
60
80
100
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
Fig.8. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
40
RDS(ON)/mOhm
a
BUK959-60
Rds(on) normlised to 25degC
2.5
35
VGS/V =
4
4.2
2
30
4.4
4.6
4.8
5
1.5
25
1
20
15
0.5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
-100
-50
0
50
100
150
200
ID/A
Tmb / degC
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
Fig.9. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j ); I D = 25 A; V GS = 5 V
100
ID/A
2.5
VGS(TO) / V
BUK959-60
max.
80
2
typ.
60
1.5
min.
40
1
20
0.5
Tj/C = 175
25
0
0
1
2
3
4
5
6
7
-100
-50
0
50
100
150
200
VGS/V
Tj / C
Fig.7. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.10. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 1 mA; V DS = V GS
April 1998
4
Rev 1.000
0
22888863.001.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9624-55
Logic level FET
1E-01
Sub-Threshold Conduction
100
IF/A
1E-02
80
1E-03
2%
typ
98%
60
1E-04
40
Tj/C =
175
25
1E-05
20
1E-05
0
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
3
VSDS/V
Fig.11. Sub-threshold drain current.
I D = f(V GS) ; conditions: T j = 25 ˚C; V DS = V GS
Fig.14. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
3
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
2.5
2
1.5
Ciss
1
0.5
Coss
Crss
0
20
40
60
80
100 120 140 160 180
Tmb / C
0.01
0.1
1
10
100
VDS/V
Fig.12. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
W DSS % = f(T mb ); conditions: I D = 75 A
6
VGS/V
+
VDD
5
VDS = 14V
L
4
VDS
VDS = 44V
-
3
VGS
-ID/10 0
2
0
T.U.T.
1
RGS
R 01
shunt
0
0
5
10
15
20
25
30
QG/nC
Fig.16. Avalanche energy test circuit.
Fig.13. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); conditions: I D = 50 A; parameter V DS
W DSS =
0.5
×
LI 2
BV DSS /(
BV DSS -
V DD )
April 1998
5
Rev 1.000
×
22888863.002.png

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