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DISCRETE SEMICONDUCTORS
DATA SHEET
BST72A
N-channel vertical D-MOS
transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
337921243.017.png
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST72A
DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
vertical D-MOS transistor in TO-92
variant envelope and designed for
use in telephone ringer circuits and
for application with relay, high-speed
and line-transformer drivers.
Drain-source voltage
V DS
max.
80 V
Drain-source voltage (non-repetitive
peak; t p £
V DS(SM)
max.
100 V
2 ms)
Gate-source voltage (open drain)
V GSO
max.
20 V
Drain current (DC)
I D
max.
300 mA
Total power dissipation up to
T amb =25
P tot
max.
0.83 W
FEATURES
C
Drain-source ON-resistance
Direct interface to C-MOS, TTL,
etc.
typ.
max.
7
10
·
W
W
I D = 150 mA; V GS =5 V
R DS(on)
·
High-speed switching
Transfer admittance
I D = 200 mA; V DS =5 V
·
No second breakdown
÷ Y fs ê
typ.
150 mS
PINNING - TO-92 VARIANT
1 = source
2 = gate
3 = drain
PIN CONFIGURATION
handbook, halfpage
1
d
2
3
g
MAM146
s
Note : Various pinout configurations available.
Fig.1 Simplified outline and symbol.
April 1995
2
°
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Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST72A
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
V DS
max.
80 V
Drain-source voltage (non-repetitive peak; t p £
2 ms)
V DS(SM)
max.
100 V
Gate-source voltage (open drain)
V GSO
max.
20 V
Drain current (DC)
I D
max.
300 mA
Drain current (peak)
I DM
max.
600 mA
Total power dissipation up to T amb =25
°
C (note 1)
P tot
max.
0.83 W
Storage temperature range
T stg
- 65 to + 150
° C
Junction temperature
T j
max.
150
°
C
THERMAL RESISTANCE
From junction to ambient (note 1)
R th j-a
=
150 K/W
Note
1. Transistor mounted on printed circuit board, max. lead length 4 mm.
April 1995
3
337921243.014.png
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST72A
CHARACTERISTICS
T j =25 ° C unless otherwise specified
Drain-source breakdown voltage
I D =10 m A; V GS =0
V (BR)DS
min.
80 V
Drain-source leakage current
V DS = 60 V; V GS =0
I DSS
max.
1.0
m
A
Gate-source leakage current
V GS = 20 V; V DS =0
I GSS
max. 100 nA
Gate threshold voltage
min.
max.
1.5
3.5
V
V
I D = 1 mA; V DS = V GS
V GS(th)
Drain-source ON-resistance (see Fig.4)
typ.
max.
7
10
W
W
I D = 150 mA; V GS =5 V
R DS(on)
Transfer admittance
I D = 200 mA; V DS =5 V
÷ Y fs ê
typ.
150 mS
Input capacitance at f = 1 MHz
typ.
max.
15
30
pF
pF
V DS = 10 V; V GS =0
C iss
Output capacitance at f = 1 MHz
typ.
max.
13
20
pF
pF
V DS = 10 V; V GS =0
C oss
Feedback capacitance at f = 1 MHz
typ.
max.
3
6
pF
pF
V DS = 10 V; V GS =0
C rss
Switching times (see Figs 2 and 3)
typ.
max.
4
10
ns
ns
I D = 200 mA; V DS = 50 V; V GS = 0 to 10 V
t on
t off
typ.
max.
4
10
ns
ns
April 1995
4
337921243.015.png
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST72A
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
Fig.4 T j =25
°
C; typical values.
Fig.5 T j =25
°
C; typical values.
April 1995
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