24X02.pdf

ST24/25C02, ST24C02R

ST24/25W02

SERIAL 2K (256 x 8) EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 3V to 5.5V for ST24x02 versions

– 2.5V to 5.5V for ST25x02 versions

– 1.8V to 5.5V for ST24C02R version only

HARDWARE WRITE CONTROL VERSIONS:

ST24W02 and ST25W02

TWO WIRE SERIAL INTERFACE, FULLY I 2 C

BUS COMPATIBLE

BYTE and MULTIBYTE WRITE (up to 4

BYTES)

PAGE WRITE (up to 8 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH-UP

PERFORMANCES

ST24C/W02 are replaced by the M24C02

ST25C/W02 are replaced by the M24C02-W

ST24C02R is replaced by the M24C02-R

PSDIP8 (B)

0.25mm Frame

SO8 (M)

150mil Width

Figure 1. Logic Diagram

V CC

DESCRIPTION

This specification covers a range of 2K bits I 2 C bus

EEPROM products, the ST24/25C02, the

ST24C02R and ST24/25W02. In the text, products

are referred to as ST24/25x02, where "x" is: "C" for

Standard version and "W" for hardware Write Con-

trol version.

E0-E2

SDA

SCL

ST24x02

ST25x02

ST24C02R

Table 1. Signal Names

MODE/WC*

E0-E2

Chip Enable Inputs

SDA

Serial Data Address Input/Output

V SS

SCL

Serial Clock

AI00788D

MODE

Multibyte/Page Write Mode

(C version)

Write Control (W version)

V CC

Supply Voltage

V SS

Ground

Note: WC signal is only available for ST24/25W02 products.

November 1997

1/16

This is information on a product still in production but not recommended for new design

ST24/25C02, ST24C02R, ST24/25W02

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x02

ST25x02

ST24C02R

ST24x02

ST25x02

ST24C02R

V CC

MODE/WC

SCL

V SS

SDA

V SS

SDA

AI00789D

AI00790E

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

T A

Ambient Operating Temperature

–40 to 125

T STG

Storage Temperature

–65 to 150

T LEAD

Lead Temperature, Soldering

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

215

260

V IO

Input or Output Voltages

–0.6 to 6.5

V CC

Supply Voltage

–0.3 to 6.5

V ESD

Electrostatic Discharge Voltage (Human Body model) (2)

4000

Electrostatic Discharge Voltage (Machine model) (3)

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

3. EIAJ IC-121 (Condition C) (200pF, 0

DESCRIPTION (cont’d)

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I 2 C bus defini-

tion. This is used together with 3 chip enable inputs

(E2, E1, E0) so that up to 8 x 2K devices may be

attached to the I 2 C bus and selected individually.

The memories behave as a slave device in the I 2 C

protocol with all memory operations synchronized

by the serial clock. Read and write operations are

initiated by a START condition generated by the

bus master. The START condition is followed by a

stream of 7 bits (identification code 1010), plus one

read/write bit and terminated by an acknowledge

bit.

The ST24/25x02 are 2K bit electrically erasable

programmable memories (EEPROM), organized

as 256 x 8 bits. They are manufactured in SGS-

THOMSON’s Hi-Endurance Advanced CMOS

technology which guarantees an endurance of one

million erase/write cycles with a data retention of

40 years. The memories operate with a power

supply value as low as 1.8V for the ST24C02R only.

Both Plastic Dual-in-Line and Plastic Small Outline

packages are available.

The memories are compatible with the I 2 C stand-

ard, two wire serial interface which uses a bi-direc-

2/16

ST24/25C02, ST24C02R, ST24/25W02

Table 3. Device Select Code

Device Code

Chip Enable

Bit

Device Select

Note: The MSB b7 is sent first.

Table 4. Operating Modes (1)

Mode

RW bit

MODE

Bytes

Initial Sequence

Current Address Read

’1’

START, Device Select, RW = ’1’

Random Address Read

’0’

START, Device Select, RW = ’0’, Address,

’1’

reSTART, Device Select, RW = ’1’

Sequential Read

’1’

1 to 256

Similar to Current or Random Mode

Byte Write

’0’

START, Device Select, RW = ’0’

Multibyte Write (2)

’0’

V IH

START, Device Select, RW = ’0’

Page Write

’0’

V IL

START, Device Select, RW = ’0’

Notes: 1. X = V IH or V IL

2. Multibyte Write not available in ST24/25W02 versions.

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

Power On Reset: V CC lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V CC

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when V CC drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V CC

must be applied before applying any logic signal.

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to V CC to act as pull up (see Figure 3).

Chip Enable (E2 - E0). These chip enable inputs

are used to set the 3 least significant bits (b3, b2,

b1) of the 7 bit device select code. These inputs

may be driven dynamically or tied to V CC or V SS to

establish the device select code.

Mode (MO DE). The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at V IL or V IH for the Byte Write

mode, V IH for Multibyte Write mode or V IL for Page

Write mode. When unconnected, the MODE input

is internally read as a V IH (Multibyte Write mode).

Write C ontro l (WC). An hardware Write Control

feature (WC) is offered only for ST24W02 and

ST25W02 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycl e. The Write Contr ol sig -

nal is used to enable (WC = V IH ) or disable (WC =

V IL ) the int erna l write protection. When uncon-

nected, the WC input is internally read as V IL and

the memory area is not write protected.

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to V CC

to act as a pull up (see Figure 3).

3/16

ST24/25C02, ST24C02R, ST24/25W02

SIGNAL DESCRIPTIONS (cont’d)

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25x02

and the bus master. A STOP condition at the end

of a Read command, after and only after a No

Acknowledge, forces the standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input. During data input the ST24/25x02

sample the SDA bus signal on the rising edge of

the clock SCL. Note that for correct device opera-

tion the SDA signal must be stable during the clock

low to high transition and the data must change

ONLY when the SCL line is low.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24/25x02,

the master must initiate a START condition. Follow-

ing this, the master sends onto the SDA bus line 8

bits (MSB first) corresponding to the device select

code (7 bits) and a READ or WRITE bit.

The devices with this Write Control feature no

longer support the Multibyte Write mode of opera-

tion, however all other write modes are fully sup-

ported.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

DEVICE OPERATION

I 2 C Bus Background

The ST24/25x02 support the I 2 C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24/25x02 are always slave

devices in all communications.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25x02 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Figure 3. Maximum R L Value versus Bus Capacitance (C BUS ) for an I 2 C Bus

V CC

R L

SDA

MASTER

SCL

C BUS

V CC = 5V

100

200

300

400

C BUS (pF)

AI01100

4/16

ST24/25C02, ST24C02R, ST24/25W02

Table 5. Input Parameters (1) (T A = 25 ° C, f = 100 kHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

C IN

Input Capacitance (SDA)

C IN

Input Capacitance (other pins)

Z WCL

WC Input Impedance (ST24/25W02)

V IN

0.3 V CC

Z WCH

WC Input Impedance (ST24/25W02)

V IN

0.7 V CC

500

t LP

Low-pass filter input time constant

(SDA and SCL)

100

Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics

(T A = 0 to 70 ° C, –20 to 85 ° C or –40 to 85 ° C; V CC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

Symbol

Parameter

Test Condition

Min

Max

Unit

I LI

Input Leakage Current

V IN

V CC

I LO

Output Leakage Current

V CC

SDA in Hi-Z

V OUT

I CC

Supply Current (ST24 series)

V CC = 5V, f C = 100kHz

(Rise/Fall time < 10ns)

Supply Current (ST25 series)

V CC = 2.5V, f C = 100kHz

Supply Current (Standby)

(ST24 series)

V IN = V SS or V CC ,

V CC = 5V

100

I CC1

V IN = V SS or V CC ,

V CC = 5V, f C = 100kHz

300

Supply Current (Standby)

(ST25 series)

V IN = V SS or V CC ,

V CC = 2.5V

I CC2

V IN = V SS or V CC ,

V CC = 2.5V, f C = 100kHz

Supply Current (Standby)

(ST24C02R)

V IN = V SS or V CC ,

V CC = 3.6V

I CC3

V IN = V SS or V CC ,

V CC = 3.6V, f C = 100kHz

Supply Current (Standby)

(ST24C02R)

V IN = V SS or V CC ,

V CC = 1.8V

I CC4

V IN = V SS or V CC ,

V CC = 1.8V, f C = 100kHz

V IL

Input Low Voltage (SCL, SDA)

–0.3

0.3 V CC

V IH

Input High Voltage (SCL, SDA)

0.7 V CC

V CC + 1

V IL

Input Low Voltag e

(E0-E2, MODE, WC)

–0.3

0.5

V IH

Input High Volta ge

(E0-E2, MODE, WC)

V CC – 0.5

V CC + 1

Output Low Voltage (ST24 series)

I OL = 3mA, V CC = 5V

0.4

V OL

Output Low Voltage (ST25 series)

I OL = 2.1mA, V CC = 2.5V

0.4

Output Low Voltage

(ST24C02R)

I OL = 1mA, V CC = 1.8V

0.3

5/16

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