FDS9936A.pdf

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323063130 UNPDF
May 1998
FDS9936A
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to provide superior switching
performance and minimize on-state resistance. These devices
are particularly suited for low voltage applications such as disk
drive motor control, battery powered circuits where fast
switching, low in-line power loss, and resistance to transients
are needed.
5.5 A, 30 V. R DS(ON) = 0.040 W @ V GS = 10 V,
R DS(ON) = 0.060 W @ V GS = 4.5 V.
High density cell design for extremely low R DS(ON) .
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package
SOT-23
SuperSOT TM -6
SuperSOT TM -8
SO-8
SOT-223
SOIC-16
D2
5
4
D2
D1
D1
6
3
7
2
G2
S2
G1
8
1
SO-8
pin 1
S1
Absolute Maximum Ratings T A = 25 o C unless other wise noted
Symbol Parameter
FDS9936A
Units
V DSS
Drain-Source Voltage
30
V
V GSS
Gate-Source Voltage
±20
V
I D
Drain Current - Continuous (Note 1a)
5.5
A
- Pulsed
20
P D
Power Dissipation for Dual Operation
2
W
Power Dissipation for Single Operation (Note 1a)
1.6
(Note 1b)
1
(Note 1c)
0.9
T J ,T STG
Operating and Storage Temperature Range
-55 to 150
°C
THERMAL CHARACTERISTICS
R q JA
Thermal Resistance, Junction-to-Ambient (Note 1a)
78
°C/W
R q JC
Thermal Resistance, Junction-to-Case (Note 1)
40
°C/W
© 1998 Fairchild Semiconductor Corporation
FDS9936A Rev.B
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Electrical Characteristics ( T A = 25 O C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV DSS
Drain-Source Breakdown Voltage
V GS = 0 V, I D = 250 µA
30
V
D BV DSS / D T J Breakdown Voltage Temp. Coefficient
I D = 250 µA, Referenced to 25 o C
32
mV/ o C
I DSS
Zero Gate Voltage Drain Current
V DS = 24 V, V GS = 0 V
1
µA
T J = 55°C
10
µA
I GSSF
Gate - Body Leakage, Forward
V GS = 20 V, V DS = 0 V
100
nA
I GSSR
Gate - Body Leakage, Reverse
V GS = -20 V, V DS = 0 V
-100
nA
ON CHARACTERISTICS (Note 2)
V GS(th)
Gate Threshold Voltage
V DS = V GS , I D = 250 µA
1
1.5
3
V
D V GS(th) / D T J Gate Threshold Voltage Temp. Coefficient
I D = 250 µA, Referenced to 25 o C
-4.3
mV/ o C
R DS(ON)
Static Drain-Source On-Resistance
V GS = 10 V, I D = 5.5 A
0.03
0.04
W
T J =125°C
0.046 0.068
V GS = 4.5 V, I D = 4.5 A
0.045
0.06
I D(ON)
On-State Drain Current
V GS = 10 V, V DS = 5 V
20
A
g FS
Forward Transconductance
V DS = 5 V, I D = 4.7 A
7
S
DYNAMIC CHARACTERISTICS
C iss
Input Capacitance
V DS = 15 V, V GS = 0 V,
f = 1.0 MHz
350
pF
C oss
Output Capacitance
220
pF
C rss
Reverse Transfer Capacitance
80
pF
SWITCHING CHARACTERISTICS (Note 2)
t D(on)
Turn - On Delay Time
V DD = 10 V, I D = 1 A,
7.5
15
ns
t r
Turn - On Rise Time
V GS = 4.5 V, R GEN = 6 W
12
25
t D(off)
Turn - Off Delay Time
13
25
t f
Turn - Off Fall Time
6
15
Q g
Total Gate Charge
V DS = 15 V, I D = 5 A,
12
17
nC
Q gs
Gate-Source Charge
V GS = 10 V
2.1
Q gd
Gate-Drain Charge
2.6
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I S
Maximum Continuous Drain-Source Diode Forward Current
1.3
A
V SD
Drain-Source Diode Forward Voltage
V GS = 0 V, I S = 1.3 A (Note 2)
0.76
1.2
V
Notes:
1. R q JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R q JC is guaranteed by
design while R q CA is determined by the user's board design.
a. 78 O C/W on a 0.5 in 2
pad of 2oz copper.
b. 125 O C/W on a 0.02 in 2
pad of 2oz copper.
c. 135 O C/W on a 0.003 in 2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDS9936A Rev.B
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Typical Electrical Characteristics
20
V = 10V
GS
3
5.5V
4.5V
16
2.5
4.0V
12
V = 3.5V
GS
2
3.5V
4.0 V
8
1.5
4.5 V
3.0V
5.0V
4
6.0V
1
10V
0
0
0.5
1
1.5
2
2.5
3
0
5
10
15
20
V , DRAIN-SOURCE VOLTAGE (V)
DS
I , DRAIN CURRENT (A)
D
Figure 1. On-Region Characteristics .
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.8
0.2
I = 5.5A
D
I = 3A
D
1.6
V = 10V
GS
0.15
1.4
1.2
0.1
1
T = 125°C
J
0.05
0.8
25°C
0.6
0
-50
-25
0
25
50
75
100
125
150
2
4
6
8
10
T , JUNCTION TEMPERATURE (°C)
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 3. On-Resistance Variation with
Temperature .
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
15
40
V =5.0V
DS
10
V = 0V
GS
T = 125°C
J
12
1
25°C
9
0.1
-55°C
6
0.01
3
T = -55°C
J
25°C
0.001
125°C
0
1
2
3
4
5
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V , GATE TO SOURCE VOLTAGE (V)
GS
V , BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDS9936A Rev.B
J
SD
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Typical Electrical Characteristics (continued)
10
1000
I = 5.5A
D
V = 5V
DS
8
500
10V
C
iss
6
15V
200
C oss
4
100
2
f = 1 MHz
V = 0 V
GS
C
rss
50
0
0
2
4
6
8
10
12
14
30
Q , GATE CHARGE (nC)
g
0.1
0.2
0.5
1
2
5
10
30
V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
30
30
25
SINGLE PULSE
R =135° C/W
T = 25°C
10
q JA
A
5
20
2
1
15
0.5
V =10V
SINGLE PULSE
R = 135°C/W
T = 25°C
GS
10
0.1
0.05
5
q JA
A
A
0
0.01
0.01
0.1
0.5 1
10
50 100
300
0.1
0.2
0.5
1
2
5
10
30 50
SINGLE PULSE TIME (SEC)
V , DRAIN-SOURCE VOLTAGE (V)
DS
Figure 9. Maximum Safe Operating Area .
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5
D = 0.5
0.2
0.2
R (t) = r(t) * R
R = 135 °C/W
q JA
q JA
q JA
0.1
0.1
0.05
0.02
0.01
0.05
P(pk)
0.02
t 1
t 2
0.01
Single Pulse
0.005
T - T = P * R (t)
q JA
J
A
Duty Cycle, D = t /t
1 2
0.002
0.001
0.0001
0.001
0.01
0.1
1
10
100
300
t , TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS9936A Rev.B
1
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SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NO T SHI P OR STO RE N EAR STRO NG ELECTROSTATIC
ELECTRO MAGN ETI C, MAG NETIC O R R ADIO ACTIVE FI ELD S
TNR DATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___g ms
MAX _____________ gms
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Antistatic Cover Tape
ESD Label
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Customized
Label
F 852
NDS
9 9 5 9
SOIC (8lds) Packaging Information
Standard
(no flow code)
Pin 1
Packaging Option
L86Z
F011
D84Z
TNR
SOIC-8 Unit Orientation
Packaging type
TNR
Rail/Tube
TNR
Qty per Reel/Tube/Bag
2,500
95
4,000
500
Reel Size
13" Dia
-
13" Dia
7" Dia
Box Dimension (mm)
343x64x343 530x130x83 343x64x343
184x187x47
1,000
Max qty per Box
5,000
30,000
8,000
Weight per unit (gm)
0.0774
0.0774
0.0774
0.0774
Weight per Reel (kg)
0.6060
-
0.9696
0.1182
Note/Comments
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
F63TNLabel
F63TN Label
LOT: CBVK741B019
QTY: 2500
FSID: FDS9953A
SPEC:
ESD Label
D/C1: D9842 QTY1:
QTY2:
SPEC REV:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
640mm minimum or
80 empty pockets
Components
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
D/C2:
CPN:
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