74HC00.PDF

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CD54HC00,CD54HCT00,CD74HC00,CD74HCT00
Data sheet acquired from Harris Semiconductor
SCHS116
CD54HC00, CD54HCT00,
CD74HC00, CD74HCT00
High Speed CMOS Logic
Quad 2-Input NAND Gate
January 1998
Features
Description
• Buffered Inputs
The Harris CD54HC00, CD54HCT00, CD74HC00 and
CD74HCT00 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
[ /Title
(CD54
HC00,
CD54
HCT00
,
CD74
HC00,
CD74
HCT00
)
/Sub-
• Typical Propagation Delay: 7ns at V CC = 5V,
C L = 15pF, T A = 25 o C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55 o C to 125 o C
Ordering Information
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
( o C)
PKG.
NO.
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
PACKAGE
CD74HC00E
-55 to 125
14 Ld PDIP
E14.3
• Alternate Source is Philips/Signetics
CD74HCT00E
-55 to 125
14 Ld PDIP
E14.3
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N IL = 30%, N IH = 30% of V CC
at V CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V IL = 0.8V (Max), V IH = 2V (Min)
- CMOS Input Compatibility, I l £ 1 m A at V OL , V OH
• Related Literature
- CD54HC00F3A and CD54HCT00F3A Military
Data Sheet, Document Number 3753
CD74HC00M
-55 to 125
14 Ld SOIC
M14.15
CD74HCT00M
-55 to 125
14 Ld SOIC
M14.15
CD54HC00F
-55 to 125
14 Ld CERDIP F14.3
CD54HCT00F
-55 to 125
14 Ld CERDIP F14.3
CD54HC00W
-55 to 125
Wafer
CD54HCT00W
-55 to 125
Wafer
CD54HC00H
-55 to 125
Die
CD54HCT00H
-55 to 125
Die
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
Pinout
CD54HC00, CD54HCT00, CD74HC00, CD74HCT00
(PDIP, CERDIP, SOIC)
TOP VIEW
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
File Number 1464.2
1
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CD54HC00, CD54HCT00, CD74HC00, CD74HCT00
Functional Diagram
1A
1
14
V CC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
TRUTH TABLE
INPUTS
OUTPUT
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
Logic Symbol
nA
nY
nB
2
314974727.001.png 314974727.002.png 314974727.003.png 314974727.004.png
CD54HC00, CD54HCT00, CD74HC00, CD74HCT00
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I IK
For V I < -0.5V or V I > V CC + 0.5V . . . . . . . . . . . . . . . . . . . . . . ± 20mA
DC Output Diode Current, I OK
For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . . ± 20mA
DC Output Source or Sink Current per Output Pin, I O
For V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . . ± 25mA
DC V CC or Ground Current, I CC or I GND . . . . . . . . . . . . . . . . . . ± 50mA
Thermal Resistance (Typical, Note 1)
q JA ( o C/W)
q JC ( o C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
CERDIP Package . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . 180 N/A
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 o C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 o C
Maximum Storage Temperature Range . . . . . . . . . .-65 o C to 150 o C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 o C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T A ) . . . . . . . . . . . . . . . . . . . . . -55 o C to 125 o C
Supply Voltage Range, V CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V I , V O . . . . . . . . . . . . . . . . . 0V to V CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
q JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
25 o C
-40 o C TO 85 o C
-55 o C TO 125 o C
PARAMETER
SYMBOL
V I (V) I O (mA)
V CC (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
High Level Input
Voltage
V IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V OH
V IH or
V IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V OL
V IH or
V IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I I
V CC or
GND
-
6
-
-
± 0.1
-
± 1
-
± 1
m A
3
NOTE:
1.
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CD54HC00, CD54HCT00, CD74HC00, CD74HCT00
DC Electrical Specifications (Continued)
TEST
CONDITIONS
25 o C
-40 o C TO 85 o C
-55 o C TO 125 o C
PARAMETER
SYMBOL
V I (V) I O (mA)
V CC (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Quiescent Device
Current
I CC
V CC or
GND
0
6
-
-
2
-
20
-
40
m
A
HCT TYPES
High Level Input
Voltage
V IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V OH
V IH or
V IL
-
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage CMOS Loads
V OL
V IH or
V IL
-4
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
0.02
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I I
V CC
and
GND
4
5.5
-
±
0.1
-
±
1
-
±
1
m
A
Quiescent Device
Current
I CC
V CC or
GND
0
5.5
-
-
2
-
20
-
40
m A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
D
I CC
V CC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
m
A
NOTE:
2. For dual-supply systems theorectical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nA
1.8
nB
1.1
NOTE: Unit Load is
D
I CC limit specified in DC Electrical Specifica-
A max at 25 o C.
tions table, e.g. 360
m
Switching Specifications Input t r , t f = 6ns
TEST
CONDITIONS
V CC
(V)
25 o C
-40 o C TO 85 o C -55 o CTO125 o C
PARAMETER
SYMBOL
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t PLH , t PHL C L = 50pF
2
-
-
90
-
115
-
135
ns
4.5
-
-
18
-
23
-
27
ns
6
-
-
15
-
20
-
23
ns
Propagation Delay, Data Input to
Output Y
t PLH , t PHL C L = 15pF
5
-
7
-
-
-
-
-
pF
4
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CD54HC00, CD54HCT00, CD74HC00, CD74HCT00
Switching Specifications Input t r , t f = 6ns (Continued)
TEST
CONDITIONS
V CC
(V)
25 o C
-40 o C TO 85 o C -55 o CTO125 o C
PARAMETER
SYMBOL
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Transition Times (Figure 1)
t TLH , t THL C L = 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C PD
-
5
-
25
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t PLH , t PHL C L = 50pF
4.5
-
-
20
-
25
-
30
ns
Propagation Delay, Data Input to
Output Y
t PLH , t PHL C L = 15pF
5
-
8
-
-
-
-
-
pF
Transition Times (Figure 2)
t TLH , t THL C L = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C PD
-
5
-
25
-
-
-
-
-
pF
NOTES:
3. C PD is used to determine the dynamic power consumption, per gate.
4. P D = V CC 2 f i (C PD + C L ) where f i = input frequency, C L = output load capacitance, V CC = supply voltage.
Test Circuits and Waveforms
t r = 6ns
t f = 6ns
t r = 6ns
t f = 6ns
90%
50%
10%
V CC
2.7V
1.3V
0.3V
3V
INPUT
INPUT
GND
GND
t THL
t TLH
t THL
t TLH
90%
90%
INVERTING
OUTPUT
50%
10%
INVERTING
OUTPUT
1.3V
10%
t PHL
t PLH
t PHL
t PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
INPUT LEVEL
HC TYPES
HCT TYPES
V CC
3V
V S
50% V CC
1.3V
NOTE: Transition times and propagation delay times.
5
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