4031.pdf

(241 KB) Pobierz
64-STAGE STATIC SHIFT REGISTER
HCC/HCF4031B
. FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ V DD –V SS = 15V
64-STAGE STATIC SHIFT REGISTER
. STANDARD TTL DRIVE CAPABILITY ON Q
. THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
DELAYED CLOCKING FOR REDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
EY
(Plastic Package)
F
(Ceramic Package)
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. STANDARDIZED, SYMMETRICAL OUTPUT
. 5V, 10V, AND 15V PARAMETRIC RATINGS
C1
(Chip Carrier)
. INPUT CURRENT OF 100nA at 18V AND 25 ° C
FOR HCC DEVICE
CHARACTERISTICS
. 100% TESTED FOR QUIESCENT CURRENT
ORDER CODES :
HCC4031BF
HCF4031BEY
HCF4031BC1
. MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N O . 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
PIN CONNECTIONS
DESCRIPTION
The HCC4031B (extended temperature range) and
HCF4031B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The HCC/HCF4031B is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be per-
manently stored with the clock line in either the low
or high state. The HCC/HCF4031B has a MODE
CONTROL input that, when in the high state, allows
operation in the recirculating mode. The MODE
CONTROL input can also be used to select between
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output (CL D ) is provided that enables cascading reg-
June 1989
1/12
. RECIRCULATION CAPABILITY
OUTPUT
21704624.002.png
HCC/HCF4031B
ister packages while allowing reduced clock drive
fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from
the 1/2 stage, which is available on the next nega-
tive-going transition of the clock after the Q output
occurs. This delayed output, like the delayed clock
CL D , is used with clocks having slow rise and fall
times.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V DD *
Supply Voltage : HCC Types
HCF Types
– 0.5 to + 20
– 0.5 to + 18
V
V
V I
Input Voltage
– 0.5 to V DD + 0.5
V
I I
DC Input Current (any one input)
±
10
mA
P tot
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T op = Full Package-temperature Range
200
mW
100
mW
T op
Operating Temperature : HCC Types
HCF Types
– 55 to + 125
–40to+85
C
°
C
T stg
Storage Temperature
– 65 to + 150
°
C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at theseor any other conditions abovethose indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to V SS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V DD
Supply Voltage : HCC Types
HCF Types
3to+18
3to+15
V
V
V I
Input Voltage
0 to V DD
V
T op
Operating Temperature : HCC Types
HCF Types
– 55 to + 125
–40to+85
C
°
C
2/12
°
°
21704624.003.png
HCC/HCF4031B
LOGIC DIAGRAM AND TRUTH TABLES
INPUT CONTROL CIRCUIT
Data
Recirc.
Mode
Bit Into
Stage 1
1
X
0
1
0
X
0
0
X
1
1
1
X
0
1
0
TYPICAL STAGE
OUTPUT FROM Q’ (pin 5)
Data
CL
Data + 1
Data + 64
CL
Data + 64.5
0
–
0
0
– \ –
0
1
–
1
1
– \ –
1
X
– \ –
NC
X
–
NC
1 = HIGH LEVEL
0 = LOW LEVEL
NC = NO CHANGE
X = DON’T CARE
3/12
21704624.004.png
HCC/HCF4031B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditions
Value
Symbol
Parameter
V I
V O
|I O |V DD
T Low *
25
°
C
T Hi g h *
Unit
(V)
(V)
(
m
A) (V) Min. Max. Min. Typ. Max. Min. Max.
I L
Quiescent
Current
0/ 5
5
5
0.04
5
150
HCC
Types
0/10
10
10
0.04 10
300
0/15
15
20
0.04 20
600
0/20
20
100
0.08 100
3000
m
A
HCF
Types
0/ 5
5
20
0.04 20
150
0/10
10
40
0.04 40
300
0/15
15
80
0.04 80
600
V OH
Output High
Voltage
0/ 5
0/10
0/15
<1
<1
<1
5
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
V OL
Output Low
Voltage
5/0
10/0
15/0
<1
<1
<1
5
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
V IH
Input High
Voltage
0.5/4.5
1/9
1.5/13.5
<1
<1
<1
5
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
V IL
Input Low
Voltage
4.5/0.5
9/1
13.5/1.5
<1
<1
<1
5
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
I OH
Output
Source
Current
(Source)
Q, Q, Q
CL D
0/ 5
2.5
5
– 2
– 1.6 – 3.2
– 1.15
HCC
Types
0/ 5
4.6
5 – 0.64
– 0.51 – 1
– 0.36
0/10
9.5
10 – 1.6
– 1.3 – 2.6
– 0.9
0/15 13.5
15 – 4.2
– 3.4 – 6.8
– 2.4
mA
0/ 5
2.5
5 – 1.53
– 1.36 – 3.2
– 1.1
HCF
Types
0/ 5
4.6
5 – 0.52
– 0.44 – 1
– 0.36
0/10
9.5
10 – 1.3
– 1.1 – 2.6
– 0.9
0/15 13.5
15 – 3.6
– 3.0 – 6.8
– 2.4
I OL
Output
Sink
Current Q
HCC
Types
0/ 5
0.4
5
2.56
2.04
4
1.44
0/10
0.5
10
6.4
5.2 10.4
3.6
0/15
1.5
15 16.8
13.6 27.2
9.6
mA
0/ 5
0.4
5
2.08
1.74
4
1.43
HCF
Types
0/10
0.5
10 5.01
4.42 10.4
3.74
0/15
1.5
15 13.6
11.56 27.2
9.52
I OL
Output
Sink
Current
Q, Q’
CL D
HCC
Types
0/ 5
0.4
5
0.64
0.51
1
0.36
0/10
0.5
10
1.6
1.3
2.6
0.9
0/15
1.5
15
4.2
3.4
6.8
2.4
mA
0/ 5
0.4
5
0.52
0.44
1
0.36
HCF
Types
0/10
0.5
10
1.3
1.1
2.6
0.9
0/15
1.5
15
3.6
3.0
6.8
2.4
I IH ,I IL Input
Leakage
Current
HCC
Types
0/18
18
±
0.1
±
10 –5
±
0.1
±
1
Any Input
m
A
HCF
Types
0/15
15
±
0.3
±
10 –5
±
0.3
±
1
C I
Input Capacitance
Any Input
5
7.5
pF
*T Low =–55
C for HCC device : – 40
°
C for HCF device.
C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with V DD = 5V, 2V min. with V DD = 10V, 2.5 V min. with V DD = 15V.
°
Cfor HCC device : + 85
°
4/12
°
*T High = + 125
21704624.005.png
HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb =25
°
C, C L = 50pF, R L = 200k
W
,
typical temperature coefficient for all V DD values is 0.3%/
°
C, all input rise and fall times = 20ns)
Symbol
Parameter
Test Conditions
Value
Unit
V DD (V) Min. Typ. Max.
t PHL ,
t PL H ,t PLH
Propagation Delay Time :
Clock to Q,
Clock to Q
5
250
500
10
110
220
ns
15
90
180
t PHL ,
t PL H ,t PHL
Propagation Delay Time :
Clock to Q’
Clock to Q
5
190
380
10
80
160
ns
15
65
130
Clock to CL D
5
100
200
10
50
100
ns
15
40
80
t THL’ ,t TLH Transition Time :
(any output, except Qt THL )
5
100
200
10
50
100
ns
15
40
80
t THL
Q,
5
50
100
10
25
50
ns
15
20
40
t setup
Data Setup Time
5
30
60
10
15
30
ns
15
10
20
t hold
Data Hold Time
5
30
60
10
15
30
ns
15
10
20
t W
Clock Pulse Width
5
120
240
10
50
100
ns
15
40
80
f max
Maximum Clock Input
Frequency**
5
2
4
10
5
10
MHz
15
6
12
t r ,t f
Clock Input Rise or Fall Time*
5
1000
10 1000
15 200
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmiti on time of the output driving stage.
* * Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
fmax = 1
m
s
(n-1) CLD prop. delay + Q prop. delay + set-up time where n = nimber of packages
b) Not Usng Delaye Clock :
fmax =
1
propagation delay + set-up time
5/12
21704624.001.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin