74107.PDF

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DUAL J-K FLIP FLOP WITH CLEAR
M54HC107
M74HC107
. HIGH SPEED
f MAX = 75 MHz (TYP.) AT V CC =5V
DUAL J-K FLIP FLOP WITH CLEAR
. HIGH NOISE IMMUNITY
V NIH =V NIL =28%V CC (MIN.)
I CC =2
A (MAX.) AT T A =25
°
C
. OUTPUT DRIVE CAPABILITY
. SYMMETRICAL OUTPUT IMPEDANCE
z
10 LSTTL LOADS
B1R
(Plastic Package)
F1R
(Ceramic Package)
. BALANCED PROPAGATION DELAYS
. WIDE OPERATING VOLTAGE RANGE
V CC (OPR) = 2 V TO 6 V
z
=I OL = 4 mA (MIN.)
t PLH =t PHL
. PIN AND FUNCTION COMPATIBLE WITH
M1R
(Micro Package)
C1R
(Chip Carrier)
54/74LS107
ORDER CODES :
M54HC107F1R
M74HC107M1R
M74HC107B1R
M74HC107C1R
DESCRIPTION
PIN CONNECTIONS (top view)
The M54/74HC107 is a high speed CMOS DUAL J-
K FLIP FLOP fabricated in silicon gate C 2 MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. These flip-flop are edge sensitive to the
clock input and change state on the negative going
transition of the clock pulse. Each one has inde-
pendent J, K, CLOCK, and CLEAR input and Q and
Q outputs. CLEAR is independent of the clock and
accomplished by a logic low on the input. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
NC =
No Internal
Connection
October 1992
1/11
. LOW POWER DISSIPATION
m
IOH
337930516.002.png
M54/M74HC107
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
J
K
CK
Q
Q
L
X
X
X
L
H
CLEAR
H
L
L
Q n
Q n
NO CHANGE
H
L
H
L
H
H
H
L
H
L
H
H
H
Q n
Q n
TOGGLE
H
X
X
Q n
Q n
NO CHANGE
X: Don’t Care
PIN DESCRIPTION
IEC LOGIC SYMBOL
PIN No
SYMBOL
NAME AND FUNCTION
1, 8, 4, 11 1J, 2J, 1K,
2K
Synchronous Inputs;
Flip-Flop 1 And 2
2, 6
1Q, 2Q
Complement Flip-Flop
Outputs
3, 5
1Q, 2Q
True Flip-Flop Outputs
12, 9
1CK, 2CK Clock Input
13, 10
1CLR,
2CLR
Asynchronous Reset
Inputs
7
GND
Ground (0V)
14
V CC
Positive Supply Voltage
LOGIC DIAGRAM (1/2 Package)
2/11
337930516.003.png
M54/M74HC107
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V CC
Supply Voltage
-0.5 to +7
V
V I
DC Input Voltage
-0.5 to V DD + 0.5
V
V O
DC Output Voltage
-0.5 to V DD + 0.5
V
I IK
DC Input Diode Current
±
20
mA
I OK
DC Output Diode Current
±
20
mA
I O
DC Output Source Sink Current Per Output Pin
±
25
mA
I CC or I GND DC V CC or Ground Current
±
50
mA
P D
Power Dissipation
500 (*)
mW
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
Storage Temperature
-65 to +150
@
65 o C derate to 300 mW by 10mW/ o C: 65 o Cto85 o C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V CC
Supply Voltage
2 to 6
V
V I
Input Voltage
0 to V CC
V
V O
Output Voltage
0 to V CC
V
T op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o C
o C
t r ,t f
Input Rise and Fall Time
V CC = 2 V
0 to 1000
ns
V CC = 4.5 V
0 to 500
V CC = 6 V
0 to 400
3/11
T stg
337930516.004.png
M54/M74HC107
DC SPECIFICATIONS
Test Conditions
Value
Symbol
Parameter
V CC
(V)
-55 to 125 o C
54HC
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85 o C
74HC
Unit
V IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
4.5
1.35
1.35
1.35
V
6.0
1.8
1.8
1.8
V OH
High Level
Output Voltage
2.0
V I =
V IH
or
V IL
1.9
2.0
1.9
1.9
4.5
I O =-20
m
A
4.4
4.5
4.4
4.4
V
6.0
5.9
6.0
5.9
5.9
4.5
I O =-4.0 mA 4.18 4.31
4.13
4.10
6.0
I O =-5.2 mA 5.68
5.8
5.63
5.60
V OL
Low Level Output
Voltage
2.0
V I =
V IH
or
V IL
0.0
0.1
0.1
0.1
I O =20
m
A
4.5
0.0
0.1
0.1
0.1
V
6.0
0.0
0.1
0.1
0.1
4.5
I O = 4.0 mA
0.17 0.26
0.33
0.40
6.0
I O = 5.2 mA
0.18 0.26
0.33
0.40
I I
Input Leakage
Current
6.0
V I =V CC or GND
±
0.1
±
±
1
m
A
I CC
Quiescent Supply
Current
6.0 V I =V CC or GND
2
20
40
m
A
4/11
T A =25 o C
54HC and 74HC
1
337930516.005.png
M54/M74HC107
AC ELECTRICAL CHARACTERISTICS (C L =50pF,Inputt r =t f =6ns)
Test Conditions
Value
Symbol
Parameter
V CC
(V)
-55 to 125 o C
54HC
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85 o C
74HC
Unit
t TLH
t THL
Output Transition
Time
2.0
30
75
95
110
4.5
8
15
19
22
ns
6.0
7
13
16
19
t PLH
t PHL
Propagation
Delay Time
(CK - Q, Q)
2.0
48
125
155
190
4.5
14
25
31
38
ns
6.0
12
21
26
32
t PLH
t PHL
Propagation
Delay Time
(CLR - Q, Q)
2.0
52
140
175
210
ns
4.5
15
28
35
42
6.0
13
24
30
36
f MAX
Maximum Clock
Frequency
2.0
6.2
23
5.0
4.2
MHz
4.5
31
70
25
21
6.0
37
80
30
25
t W(H)
t W(L)
Minimum Pulse
Width
(CLOCK)
2.0
20
75
95
110
4.5
5
15
19
22
ns
6.0
4
13
16
19
t W(L)
Minimum Pulse
Width
(CLR)
2.0
20
75
95
110
4.5
5
15
19
22
ns
6.0
4
13
16
19
t s
Minimum Set-up
Time
2.0
28
75
95
110
4.5
7
15
19
22
ns
6.0
6
13
16
19
t h
Minimum Hold
Time
2.0
0
0
0
4.5
0
0
0
ns
6.0
0
0
0
t REM
Minimum
Removal Time
(CLR)
2.0
25
30
40
ns
4.5
5
6
8
6.0
5
5
7
C IN
Input Capacitance
5
10
10
10
pF
C PD (*) Power Dissipation
Capacitance
32
pF
(*) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I CC (opr) = C PD
•
V CC
•
f IN +I CC /2 (per FLIP/FLOP)
5/11
T A =25 o C
54HC and 74HC
337930516.001.png

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