29C010.pdf

Features

• Fast Read Access Time - 70 ns

• 5-Volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)

– 1024 Sectors (128 bytes/sector)

– Internal Address and Data Latches for 128 Bytes

• Two 8K Bytes Boot Blocks with Lockout

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Fast S ector Program Cycle Time - 10 ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

1-Megabit

(128K x 8)

5-volt Only

Flash Memory

Description

The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read

only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by 8

bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device

offers access times to 70 ns with power dissipation of just 275 mW over the commer-

cial temperature range. When the device is deselected, the CMOS standby current is

less than 100

AT29C010A

µA. The device endurance is such that any sector can typically be writ-

ten to in excess of 10,000 times.

(continued)

Pin Configurations

DIP Top View

Pin Name

Function

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A1 1

A1 0

I/O7

I/O6

I/O5

I/O4

I/O3

A0 - A16

Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O7

Data Inputs/Outputs

No Connect

TSOP Top View

Type 1

PLCC Top View

A11

A13

A14

VCC

A16

A15

A12

A1 0

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

A14

A13

A1 1

A1 0

I/O7

Rev. 0394B–10/98

To allow for simple in-system reprogrammability, the

AT29C010A does not require high input voltages for pro-

gramming. Five-volt-only commands determine the opera-

tion of the device. Reading data out of the device is similar

to reading from an EPROM. Reprogramming the

AT29C010A is performed on a sector basis; 128 bytes of

data are loaded into the device and then simultaneously

programmed.

During a reprogram cycle, the address locations and 128

bytes of data are internally latched, freeing the address and

data bus for other operations. Following the initiation of a

program cycle, the device will automatically erase the sec-

tor and then program the latched data using an internal

co ntrol ti mer. The end of a program cycle can be detected

by DATA polling of I/O7. Once the end of a program cycle

has been detected, a new access for a read or program

can begin.

programmed during the internal programming period. After

the first data byte has been loaded into the device, succes-

sive bytes are entered in the same manner. Each new byte

to b e p rogr ammed must have its high to low transitio n on

WE (or CE) within 150

s of the last low to high transition,

the load period will end and the internal programming

period will start. A7 to A16 specify the sector address. The

sector add res s m ust be valid during each high to low transi-

tion of WE (or CE). A0 to A6 specify the byte address within

the sector. The bytes may be loaded in any order; sequen-

tial loading is not required. Once a programming operation

has been initiated, and for the duration of t WC , a read oper-

ation will effectively be a polling operation.

SOFTWARE DATA PROTECTION: A software con-

trolled data protection feature is available on the

AT29C010A. Once the software protection is enabled a

software algorithm must be issued to the device before a

program may be performed. The software protection fea-

ture may be enabled or disabled by the user; when shipped

from Atmel, the software data protection feature is dis-

abled. To enable the software data protection, a series of

three program commands to specific addresses with spe-

cific data must be performed. After the software data pro-

tection is enabled the same three program commands

must begin each program cycle in order for the programs to

occur. All software program commands must obey the sec-

tor program timing specifications. Once set, the software

data protection feature remains active unless its disable

command is issued. Power transitions will not reset the

software data protection feature, however the software fea-

ture will guard against inadvertent program cycles during

power transitions.

Once set, software data protection will remain active unless

the disable command sequence is issued.

After setting SDP, any attempt to write to the device without

the 3-byte command sequence will start the internal write

timers. No data will be written to the device; however, for

the duration of t WC , a read operation will effectively be a

polling operation.

After the software data protection’s 3-byte command code

is give n, a byt e lo ad is perfor me d b y ap plying a low pulse

on t he WE or CE input with CE or WE low (respectively)

and O E hig h. The address is latched on the falling edge of

CE or WE, whichever occu rs last . The data is latched by

the first rising edge of CE or WE. The 128 bytes of data

must be loaded into each sector by the same procedure as

outlined in the program section under device operation.

HARDWARE DATA PROTECTION: Hardware features

protect against inadvertent programs to the AT29C010A in

the following ways: (a) V CC sense—if V CC is below 3.8V

(typical), the program function is inhibited; (b) V CC power on

Block Diagram

Device Operation

READ : The AT2 9C010A is acce ssed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. T he ou tpu ts are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

BYTE LOAD: Byte loads are used to enter the 128 bytes

of a sector to be programmed or the software codes for

data protecti on. A by te l oad is perf orm ed by a pplying a low

pulse on th e W E or CE input with CE or WE low (respec-

tively) a nd O E high . The address is latched on the falling

edge of CE or WE, whichever occ ur s la st. The data is

latched by the first rising edge of CE or WE.

PROGRAM: The device is reprogrammed on a sector

basis. If a byte of data within a sector is to be changed,

data for the entire sector must be loaded into the device.

The data in any byte that is not loaded during the program-

ming of its sector will be indeterminate. Once the bytes of a

sector are loaded into the device, they are simultaneously

AT29C010A

s of the low to high transition of WE

(or CE) of the preceding byte. If a high to low transition is

not detected within 150

AT29C010A

delay—once V CC has reached the V CC sense level, the

device will automatically time out 5 ms (typical) bef ore pro-

gra mming; (c) P rogram inhibit—holding any one of OE low,

CE high or WE high inhibits program cycles; an d (d) No ise

filter—pulses of less than 15 ns (typical) on the WE or CE

inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION: The product identification

mode identifies the device and manufacturer as Atmel. It

may be accessed by hardware or software operation. The

hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for

the Atmel product. In addition, users may wish to use the

software product identification mode to identify the part (i.e.

using the device code), and have the system software use

the appropriate sector size for program operations. In this

manner, the user can have a common board design for

256K to 4-megabit densities and, with each density’s sector

size in a memory map, have the system software apply the

appropriate sector size.

For details, see Operating Modes (for hardware operation)

or Software Product Identification. The manufacturer and

device code is the same for both modes.

DATA POLLING: The AT29C010A features DATA poll-

ing to indicate the end of a program cycle. During a pro-

gram cycle an attempted read of the last byte loaded will

result in the complement of the loaded data on I/O7. Once

the program cycle has been completed, true data is valid

on all outputs and the next cycle may begin. DATA polling

may begin at any time during the prog ram cyc le.

TOGGLE BIT: In addition to DATA polling the

AT29C010A provides another method for determining the

end of a program or erase cycle. During a program or erase

operation, successive attempts to read data from the

device will result in I/O6 toggling between one and zero.

Once the program cycle has completed, I/O6 will stop tog-

gling and valid data will be read. Examining the toggle bit

may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device can

be erased by using a 6-byte software code. Please see

Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT: The

AT29C010A has two designated memory blocks that have

a programming lockout feature. This feature prevents pro-

gramming of data in the designated block once the feature

has been enabled. Each of these blocks consists of 8K

bytes; the programming lockout feature can be set inde-

pendently for either block. While the lockout feature does

not have to be activated, it can be activated for either or

both blocks.

These two 8K memory sections are referred to as boot

blocks. Secure code which will bring up a system can be

contained in a boot block. The AT29C010A blocks are

located in the first 8K bytes of memory and the last 8K

bytes of memory. The boot block programming lockout fea-

ture can therefore support systems that boot from the lower

addresses of memory or the higher addresses. Once the

programming lockout feature has been activated, the data

in that block can no longer be erased or programmed; data

in other memory locations can still be changed through the

regular programming methods. To activate the lockout fea-

ture, a series of seven program commands to specific

addresses with specific data must be performed. Please

see Boot Block Lockout Feature Enable Algorithm.

If the boot block lockout feature has been activated on

either block, the chip erase function will be disabled.

BOOT BLOCK LOCKOUT DETECTION: A software

method is available to determine whether programming of

either boot block section is locked out. See Software Prod-

uct Identification Entry and Exit sections. When the device

is in the software product identification mode, a read from

location 00002 will show if programming the lower address

boot block is locked out while reading location FFFF2 will

do so for the upper boot block. If the data is FE, the corre-

sponding block can be programmed; if the data is FF, the

program lockout feature has been activated and the corre-

sponding block cannot be programmed. The software prod-

uct identification exit mode should be used to return to

standard operation.

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55 ° C to +125 ° C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature ..................................... -65 ° C to +150 ° C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V CC + 0.6V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

DC and AC Operating Range

AT29C010A-70

AT29C010A-90

AT29C010A-12

AT29C010A-15

Operating

Temperature (Case)

Com.

0 ° C - 70 ° C

Ind.

-40 ° C - 85 ° C

V CC Power Supply

5V ± 5%

5V ± 10%

Operating Modes

Mode

I/O

Read

V IL

V IH

D OUT

Program (2)

V IL

V IH

V IL

D IN

5V Chip Erase

V IL

V IH

V IL

Standby/Write Inhibit

V IH

X (1)

High Z

Program Inhibit

V IH

Program Inhibit

V IL

Output Disable

V IH

High Z

Product Identification

Hardware

V IL

V IH

A1 - A16 = V IL , A9 = V H , (3) A0 = V IL

Manufacturer Code (4)

A1 - A16 = V IL , A9 = V H , (3) A0 = V IH

Device Code (4)

Software (5)

A0 = V IL

Manufacturer Code (4)

A0 = V IH

Device Code (4)

Notes: 1. X can be V IL or V IH .

2. Refer to AC Programming Waveforms.

3. V H = 12.0V

0.5V.

4. Manufacturer Code: 1F, Device Code: 5D.

5. See details under Software Product Identification

Entry/Exit.

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

I LI

Input Load Current

V IN = 0V to V CC

m A

I LO

Output Leakage Current

V I/O = 0V to V CC

m A

0° - 40°C

m A

I SB1

V CC Standby Current CMOS CE = V CC - 0.3V to V CC

Com.

100

m A

Ind.

300

m A

I SB2

V CC Standby Current TTL

CE = 2.0V to V CC

I CC

V CC Active Current

f = 5 MHz; I OUT = 0 mA

V IL

Input Low Voltage

0.8

V IH

Input High Voltage

2.0

V OL

Output Low Voltage

I OL = 2.1 mA

0.45

V OH1

Output High Voltage

I OH = -400 m A

2.4

V OH2

Output High Voltage CMOS

I OH = -100 m A; V CC = 4.5V

4.2

AT29C010A

AT29C010A

AC Read Characteristics

AT29C010A-70 AT29C010A-90 AT29C010A-12 AT29C010A-15

Symbol Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Units

t ACC

Address to Output Delay

120

150

t CE (1)

CE to Output Delay

120

150

t OE (2)

OE to Output Delay

t DF (3)(4)

CE or OE to Output Float

t OH

Output Hold from OE, CE or

Address, whichever occurred first

AC Read Waveforms (1)(2)(3)(4)

Notes: 1. CE may be delayed up to t ACC - t CE after the address tran sitio n without impact on t ACC .

2. OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE or by t ACC - t OE after an address change

without impact on t A CC .

3. t DF is specified from OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Measurement Level

Output Test Load

70 ns

90/120/150 ns

t R , t F < 5 ns

Pin Capacitance

f = 1 MHz, T = 25°C (1)

Symbol

Typ

Max

Units

Conditions

C IN

V IN = 0V

C OUT

V OUT = 0V

Note: 1. This parameter is characterized and is not 100% tested.

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