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INTEGRATED CIRCUITS
DATA SHEET
SAA7707H
Car radio Digital Signal Processor
(CDSP)
Preliminary specication
File under Integrated Circuits, IC01
1996 May 22
389383566.012.png
Philips Semiconductors
Preliminary specication
Car radio Digital Signal Processor
(CDSP)
SAA7707H
CONTENTS
9.9
Clock circuit and oscillator
9.10
Crystal oscillator supply
1
FEATURES
9.11
External control pins
1.1
Hardware
10
I 2 S-BUS DESCRIPTION
1.2
Software
10.1
I 2 C-bus control (SCL and SDA pins)
2
APPLICATIONS
10.2
I 2 S-bus description
3
GENERAL DESCRIPTION
10.3
Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)
4
QUICK REFERENCE DATA
10.4
Communication with external processors and
other devices (EXWS/CL/EXDAT1 and
EXDAT2)
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
10.5
Relationship between external input and
external output
7
PINNING
8
FUNCTIONAL DESCRIPTION
10.6
RDS decoder (RDSCLK and RDSDAT)
8.1
Signal path for level information
10.7
Clock and data recovery
8.2
Level ADC switch mode integrator (pin CINT)
10.8
Timing of clock and data signals
8.3
Internal ground reference for the level ADC
(pin V DACNL )
10.9
Buffering of RDS data
10.10
Buffe r interface
8.4
Common mode reference voltage for RDS
ADC, ADC level and buffers (pin V refRDS )
10.11
DSP reset
10.12
Power supply connection and EMC
8.5
Signal path for audio/MPX and stereo decoder
11
LIMITING VALUES
8.6
Mono/stereo switching
12
THERMAL CHARACTERISTICS
8.7
The automatic lock system
8.8
Input sensitivity for FM
13
DC CHARACTERISTICS
8.9
Common mode reference voltage for MPX
ADC and buffers (pin V refMPX )
14
AC CHARACTERISTICS
15
I 2 C-BUS CONTROL AND COMMANDS
8.10
Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins V DACNM and V DACPM )
15.1
Characteristics of the I 2 C-bus
15.2
Bit transfer
8.11
Noise level
15.3
START and STOP conditions
8.12
TAPE/AUX de-multiplex
15.4
Data transfer
8.13
Signal-to-noise considerations
15.5
Acknowledge
8.14
Channel separation correction
15.6
I 2 C-bus format
8.15
Input selection switches
16
SOFTWARE DESCRIPTION
8.16
Analog inputs supply
17
APPLICATION INFORMATION
8.17
Digitally controlled sampling clock (DCS)
8.18
Survey of the DCS clock settings in different
modes
18
PACKAGE OUTLINE
19
SOLDERING
8.19
Synchronization with the core
19.1
Introduction
8.20
Interference absorption circuit
19.2
Reflow soldering
8.21
IAC testing
19.3
Wave soldering
9
ANALOG OUTPUTS
19.4
Repairing soldered joints
9.1
Digital-to-Analog Converters
20
DEFINITIONS
9.2
Upsample filter
21
LIFE SUPPORT APPLICATIONS
9.3
Volume control
22
PURCHASE OF PHILIPS I 2 C COMPONENTS
9.4
Power-on mute
9.5
Power-off plop suppression
9.6
Internal reference buffer amplifier of the DAC
(pin V ref )
9.7
Internal DAC current reference
9.8
Analog outputs supply
1996 May 22
2
389383566.013.png 389383566.014.png 389383566.015.png 389383566.001.png
Philips Semiconductors
Preliminary specication
Car radio Digital Signal Processor (CDSP)
SAA7707H
1 FEATURES
2 APPLICATIONS
1.1
Hardware
·
Car radio
·
Bitstream 3rd-order Sigma-Delta Analog-to-Digital
Converters (ADCs) with anti-aliasing broadband input
filters
·
Car audio systems.
3 GENERAL DESCRIPTION
·
Digital-to-Analog Converters (DACs)with four times
oversampling and noise shaping
The SAA7707H performs all the signal functions in front of
the power amplifiers and behind the AM and FMMPX
demodulation of a car radio or the tape input.
These functions are:
·
·
Digital stereo decoder
·
Improved digital Interference Absorption Circuit (IAC)
·
RDS processing with optional 16-bit buffer via separate
channel (two-tuner radio possible)
Interference absorption
·
Stereo decoding
·
Auxiliary analog CD input (CD-walkman, speech,
economic CD-changer, etc.)
·
RDS decoding
·
FM and AM weak signal processing (soft mute, sliding
stereo, etc.)
·
Two separate full I 2 S-bus CD and DCC high
performance interfaces
·
Dolby-B tape noise reduction
·
Expandable with additional Digital Signal Processors
(DSPs) for sophisticated features through an I 2 S-bus
gateway
·
The audio controls (volume, balance, fader, tone and
dynamics compression).
·
Audio output short-circuit protected
Some functions have been implemented in hardware
(stereo decoder, RDS decoder and IAC) and are not freely
programmable. Digital audio signals from external sources
with I 2 S-bus formats are accepted. There are four
independent analog output channels. This enables, in
special system configurations, separate tone and
equalization control for front and rear speakers.
·
I 2 C-bus controlled
·
Analog tape input
·
Operating ambient temperature from
-
40 to +85
°
C.
1.2
Software
·
Improved FM weak signal processing
The CDSP contains a basic program that enables a set
with:
·
·
Integrated 19 kHz MPX filter and de-emphasis
AM/FM reception
·
Electronic adjustments: FM/AM level, FM channel
separation and Dolby level
·
Sophisticated FM weak signal functions
·
Baseband audio processing (treble, bass, balance,
fader and volume)
·
Music Search detection for Tape (MSS)
·
Dolby-B tape noise reduction system
·
Dynamic loudness or bass boost
·
CD play with compressor function
·
Stereo one-band parametric equalizer
Separate bass and treble tone control and fader/balance
control.
For high-end sets with special and more sophisticated
features, an additional Digital Signal Processor (DSP) can
be connected. Examples of such features are:
·
·
Audio level meter for an automatic leveller
(in combination with microcontroller)
·
Tape equalization (DCC analog playback)
·
Music Search detection for Tape (MSS)
Noise-dependent volume control
·
Pause detection for RDS updates
·
10-band graphic equalizer
·
Dolby-B tape noise reduction
·
Audio spectrum analyzer on display
·
Adjustable dynamics compressor
·
Signal delay for concert hall effects.
·
CD and DCC de-emphasis processing
·
Signal level, noise and multi-path detection for RDS
(I 2 C-bus command)
·
Improved AM reception.
1996 May 22
3
·
389383566.002.png
Philips Semiconductors
Preliminary specication
Car radio Digital Signal Processor (CDSP)
SAA7707H
4 QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V DDD(tot)
total DC supply voltage
all supply pins
4.75
5
5.5
V
I DDD(tot)
total DC supply current
maximum activity of the
DSP; f xtal = 36 MHz
-
160
200
mA
P tot
total power dissipation
maximum activity of the
DSP; f xtal = 36 MHz
-
0.8
1.1
W
S/N
level ADC signal-to-noise
ratio
RMS value;
unweighted;
B=0to29kHz;
maximum input
48
54
-
dB
ADC signal-to-noise ratio
not multiplexed;
B = 19 kHz;
V i = 1 V (RMS)
81
85
-
dB
multiplexed;
unweighted;
B = 19 kHz; 1 V (RMS)
72
76
-
dB
ADC signal-to-noise ratio for
FM-RDS
RMS value; B = 6 kHz;
unweighted; f c =57kHz
56
-
-
dB
V iFS
ADC full scale input voltage V DDA1 = 4.75 to 5.5 V
1.05V DDA1 1.1V DDA1 1.15V DDA1 V
THD
total harmonic distortion
pins 62 and 71 to 75
f i = 1 kHz;
V i = 1 V (RMS)
-
-
71
-
61
dB
-
0.03
0.09
%
V imc(rms)
maximum conversion input
voltage level pins 62 and
71 to 75 (RMS value)
THD < 1%
1.1
-
-
V
RES
DAC resolution
-
18
-
bits
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio for DAC
and operational ampliers
AC;
R fb = 2.7 k W ; f i = 1 kHz;
R ref =18k
-
-
70
-
57
dB
;
V oFS = 2.8 V (p-p);
maximum I 2 S-bus signal
W
DR
dynamic range of DAC
f i = 1 kHz;
-
60 dB;
92
102
-
dB
A-weighted
DS
digital silence of DAC
f i = 20 Hz to 17 kHz;
A-weighted
-
-
110
-
100
dB
f xtalDSP
crystal frequency DSP part
-
36.86
-
MHz
5 ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7707H
QFP80 plastic quad at package; 80 leads (lead length 1.95 mm);
body 14 x 20 x 2.8 mm
SOT318-2
1996 May 22
4
R L >5k
W
389383566.003.png
V DACNL
V SSD2
V SSD5
V SSD8
V DDD3
MUTE
MSS/P
V SSO
V DDD1
V SSG
V SSD3
V SSD6
V SSD9
V DDD4
DEEM
V DDA
V DDO
V SSA
CINT
V SSA1
V SSD1
V SSD4
V SSD7
V DDD2
V DDD5
STEREO
V DDA1
V SSD1
V DACPM
77
21
67 68
5
22
50 51
54
55
34
41
29
56
49
52
53
44
45
42
43
8
69
15
14
6
5
7
V DACNM
78
70
40
EXCLK
V refMPX
SAA7707H
80
20
V ref
V refRDS
13
62
SIGNAL
LEVEL
I ref(int)
MPXRDS
ADC
4
AM
18
FIOL
3
FM
19
FVOL
72
AUXR
16
SIGNAL
QUALITY
FIOR
74
TAPER
17
FVOR
73
ADC
TAPEL
ANALOG
SOURCE
SELECTOR
DIGITAL
SIGNAL
PROCESSOR
AUXL
71
QUADRATURE
DAC
INTERFERENCE
ABSORPTION
CIRCUIT
DIGITAL
STEREO
DECODER
75
AMAF
11
12
9
76
RIOL
RVOL
FMMPX
DIGITAL
SOURCE
SELECTOR
79
FMRDS
ADC
RIOR
10
RVOR
21
POM
DIGITALLY
CONTROLLED
SAMPLING
RDS
DECODER
CRYSTAL
OSCILLATOR
I 2 C-BUS
INTERFACE
32
33 30
66
65
60
61
64
63
23
24
25
48
47
46
59
57
58
35
36
28
27
37
38
39
31
26
MBH163
TSCAN
V DDX
V SSX
XTALO
A0
SHTCB
RDSDAT
RDSCLK
CDWS
CDCLK
XTALI
DCCWS
TEST1
EXSCL
EXWS
EXDAT1
SDA
SCL
RTCB
DCCDAT
TEST2
EXDAT
DSPRESET
CDDAT
DCCCLK
V SSD10
EXDAT2
Fig.1 Block diagram.
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