ad7893.pdf

LC 2 MOS 12-Bit, Serial 6

ADC in 8-Pin Package

AD7893

FEATURES

Fast 12-Bit ADC with 6

FUNCTIONAL BLOCK DIAGRAM

s Conversion Time

REF IN

V DD

8-Pin Mini-DlP and SOIC

Single Supply Operation

High Speed, Easy-to-Use, Serial Interface

On-Chip Track/Hold Amplifier

Selection of Input Ranges

AD7893

V IN

SIGNAL

SCALING*

TRACK/

HOLD

10 V for AD7893-10

12-BIT

ADC

2.5 V for AD7893-3

0 V to +2.5 V for AD7893-2

0 V to +5 V for AD7893-5

Low Power: 25 mW typ

CONVST

OUTPUT

AGND

DGND

SCLK

SDATA

*AD7893-5, AD7893-10, AD7893-3

GENERAL DESCRIPTION

The AD7893 is a fast, 12-bit ADC that operates from a single

+5 V supply and is housed in a small 8-pin mini-DIP and 8-pin

SOIC. The part contains a 6 ms successive approximation A/D

converter, an on-chip track/hold amplifier, an on-chip clock and

a high speed serial interface.

Output data from the AD7893 is provided via a high speed,

serial interface port. This two-wire serial interface has a serial

clock input and a serial data output with the external serial clock

accessing the serial data from the part.

In addition to traditional dc accuracy specifications such as lin-

earity, full-scale and offset errors, the AD7893 is also specified

for dynamic performance parameters, including harmonic dis-

tortion and signal-to-noise ratio.

The part accepts an analog input range of ± 10 V (AD7893-10),

± 2.5 V (AD7893-3), 0 V to +5 V (AD7893-5) or 0 V to +2.5 V

(AD7893-2) and operates from a single +5 V supply, consuming

only 25 mW typical.

The AD7893 is fabricated in Analog Devices’ Linear Compat-

ible CMOS (LC 2 MOS) process, a mixed technology process

that combines precision bipolar circuits with low power CMOS

logic. The part is available in a small, 8-pin, 0.3" wide, plastic or

hermetic dual-in-line package (mini-DIP) and in an 8-pin, small

outline IC (SOIC).

s ADC, a track/hold amplifier,

control logic and a high speed serial interface, all in an 8-pin

package. This offers considerable space saving over alterna-

tive solutions.

2. Low Power, Single Supply Operation

The AD7893 operates from a single +5 V supply and con-

sumes only 25 mW. This low power, single supply operation

makes it ideal for battery powered or portable applications.

3. High Speed Serial Interface

The part provides high speed serial data and serial clock lines,

allowing for an easy, two-wire serial interface arrangement.

REV. E

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

PRODUCT HIGHLIGHTS

1. Fast, 12-Bit ADC in 8-Pin Package

The AD7893 contains a 6

Fax: 617/326-8703

AD7893–SPECIFICATIONS

(V DD = +5 V, AGND = DGND = 0 V, REF IN = +2.5 V. All specifications T MIN to T MAX unless

otherwise noted.)

Parameter

Versions l

Versions

Version

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to (Noise + Distortion) Ratio 2

@ +25°C

dB min

f IN = 10 kHz Sine Wave, f SAMPLE = 117 kHz

Total Harmonic Distortion (THD) 2

–80

dB max

f IN = 10 kHz Sine Wave, f SAMPLE = 117 kHz

Peak Harmonic or Spurious Noise 2

–80

dB max

f IN = 10 kHz Sine Wave, f SAMPLE = 117 kHz

Intermodulation Distortion (IMD) 2

fa = 9 kHz, fb = 9.5 kHz, f SAMPLE = 117 kHz

2nd Order Terms

–80

dB max

3rd Order Terms

–80

dB max

DC ACCURACY

Resolution

Bits

Minimum Resolution for which

No Missing Codes are Guaranteed

Bits

Relative Accuracy 2

1/2

LSB max

Differential Nonlinearity 2

LSB max

Positive Full-Scale Error 2

1.5

LSB max

AD7893-2, AD7893-5

Unipolar Offset Error

LSB max

AD7893-10, AD7893-3

Negative Full-Scale Error 2

1.5

LSB max

Bipolar Zero Error

LSB max

ANALOG INPUT

AD7893-10

Input Voltage Range

± 10

Volts

Input Resistance

kW min

AD7893-3

Input Voltage Range

± 2.5

Volts

Input Resistance

kW min

AD7893-5

Input Voltage Range

0 to +5

Volts

Input Resistance

kW min

AD7893-2

Input Voltage Range

0 to +2.5

Volts

Input Current

500

nA max

REFERENCE INPUT

REF IN Input Voltage Range

2.375/2.625 2.375/2.625 2.375/2.625 V min/V max 2.5 V

Input Current

A max

Input Capacitance 3

pF max

LOGIC INPUTS

Input High Voltage, V INH

2.4

V min

V DD = 5 V ± 5%

Input Low Voltage, V INL

0.8

V max

V DD = 5 V ± 5%

Input Current, I IN

± 10

mA max

V IN = 0 V to V DD

Input Capacitance, C IN 3

pF max

LOGIC OUTPUTS

Output High Voltage, V OH

4.0

V min

I SOURCE = 200

Output Low Voltage, V OL

0.4

V max

I SINK = 1.6 mA

Output Coding

AD7893-10, AD7893-3

2s Complement

AD7893-2, AD7893-5

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

ms max

Track/Hold Acquisition Time 2

1.5

ms max

POWER REQUIREMENTS

V DD

V nom

5% for Specified Performance

I DD

mA max

Power Dissipation

mW max

Typically 25 mW

NOTES

1 Temperature Ranges are as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.

2 See Terminology.

3 Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. E

AD7893

TIMING CHARACTERISTICS 1, 2

A, B

(V DD = +5 V, AGND = DGND = 0 V, REF IN = +2.5 V)

Parameter

Versions

Version

Units

Test Conditions/Comments

t 1

ns min

CONVST Pulse Width

t 2

ns min

SCLK High Pulse Width

t 3

ns min

SCLK Low Pulse Width

t 4 3

ns max

SCLK Rising Edge to Data Valid Delay

t 5 4

ns min

Bus Relinquish Time after Falling Edge of SCLK

100

ns max

NOTES

1 Sample tested at +25

C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

2 See Figure 5.

3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 5 , quoted in the timing characteristics is the true bus relinquish time

of the part and, as such, is independent of external bus loading capacitances.

ABSOLUTE MAXIMUM RATINGS*

(T A = +25°C unless otherwise noted)

V DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to AGND

AD7893-10, AD7893-5 . . . . . . . . . . . . . . . . . . . . . . . ± 17 V

AD7893-2, AD7893-3 . . . . . . . . . . . . . . . . . . . –5 V, +10 V

Reference Input Voltage to AGND . . . –0.3 V to V DD + 0.3 V

Digital Input Voltage to DGND . . . . . –0.3 V to V DD + 0.3 V

Digital Output Voltage to DGND . . . . –0.3 V to V DD + 0.3 V

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 130°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

1.6mA

OUTPUT

+2.1V

50pF

200µA

Figure 1. Load Circuit for Access Time and Bus

Relinquish Time

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7893 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. E

–3–

AD7893

PIN FUNCTION DESCRIPTION

Pin Pin

No. Mnemonic

Description

REF IN

Voltage Reference Input. An external reference source should be connected to this pin to provide the refer-

ence voltage for the AD7893’s conversion process. The REF IN input is buffered on-chip. The nominal ref-

erence voltage for correct operation of the AD7893 is +2.5 V.

Analog Input Channel. The analog input range is ± 10 V (AD7893-10), ± 2.5 V (AD7893-3), 0 V to +5 V

(AD7893-5) and 0 V to +2.5 V (AD7893-2).

AGND

Analog Ground. Ground reference for track/hold, comparator and DAC.

SCLK

Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7893. A

new serial data bit is clocked out on the rising edge of this serial clock, and data is valid on the falling edge.

The serial clock input should be taken low at the end of the serial data transmission.

SDATA

Serial Data Output. Serial data from the AD7893 is provided at this output. The serial data is clocked out by

the rising edge of SCLK and is valid on the falling edge of SCLK. Sixteen bits of serial data are provided

with four leading zeros followed by the 12 bits of conversion data. On the sixteenth falling edge of SCLK, the

SDATA line is disabled (three-stated). Output data coding is twos complement for the AD7893-10 and

AD7893-3, straight binary for the AD7893-2 and AD7893-5.

DGND

Digital Ground. Ground reference for digital circuitry.

CONVST

Convert Start. Edge-triggered logic input. On the falling edge of this input, the serial clock counter is reset to

zero. On the rising edge of this input, the track/hold goes into its hold mode and conversion is initiated.

Positive supply voltage, +5 V ± 5%.

PIN CONFIGURATION

DIP and SOIC

REF IN

V DD

V IN

AD7893

TOP VIEW

(NOT TO SCALE)

CONVST

AGND

SCLK

DGND

SDATA

ORDERING GUIDE

Temperature

Linearity

Package

Model

Range

Error

SNR

Options*

AD7893AN-2 –40°C to +85°C

± 1 LSB

70 dB N-8

AD7893BN-2 –40°C to +85°C

± 1/2 LSB 72 dB N-8

AD7893AR-2 –40°C to +85°C

± 1 LSB

70 dB SO-8

AD7893BR-2 –40°C to +85°C

± 1/2 LSB 72 dB SO-8

AD7893SQ-2 –55°C to +125°C

± 1 LSB

70 dB Q-8

AD7893AN-5 –40°C to +85°C

± 1 LSB

70 dB N-8

AD7893BN-5 –40°C to +85°C

± 1/2 LSB 72 dB N-8

AD7893AR-5 –40°C to +85°C

± 1 LSB

70 dB SO-8

AD7893SQ-5 –55°C to +125°C

± 1/2 LSB 72 dB SO-8

70 dB Q-8

AD7893AN-10 –40°C to +85°C

± 1 LSB

70 dB N-8

AD7893BN-10 –40°C to +85°C

± 1/2 LSB 72 dB N-8

70 dB SO-8

AD7893BR-10 –40°C to +85°C

± 1/2 LSB 72 dB SO-8

AD7893SQ-10 –55°C to +125°C

± 1 LSB

70 dB Q-8

AD7893AR-3 –40°C to +85°C

± 1 LSB

70 dB SO-8

*N = Plastic DIP, Q = Cerdip, SO = SOIC.

–4–

REV. E

AD7893BR-5 –40°C to +85°C

± 1 LSB

AD7893AR-10 –40°C to +85°C

± 1 LSB

AD7893

TERMINOLOGY

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f S /2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. The theoretical signal to (noise + distortion) ratio

for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7893, it is defined as:

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7893-10)

This is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal 4 ´ REF IN – 1 LSB (AD7893-10

± 10 V range) after the Bipolar Zero Error has been adjusted out.

Positive Full-Scale Error (AD7893-3)

This is the deviation of the last code transition (01 . . . 110 to

01 . . . 111) from the ideal (REF IN – 1 LSB) after the

Bipolar Zero Error has been adjusted out.

Positive Full-Scale Error (AD7893-5)

This is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (2 ´ REF IN – 1 LSB) after the Uni-

polar Offset Error has been adjusted out.

Positive Full-Scale Error (AD7893-2)

This is the deviation of the last code transition (11 . . . 110 to

11 . . . 111) from the ideal (REF IN – 1 LSB) after the Unipolar

Offset Error has been adjusted out.

Bipolar Zero Error (AD7893-10, 6 10 V; AD7893-3, 6 2.5 V)

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal 0 V (AGND).

Unipolar Offset Error (AD7893-2, AD7893-5)

This is the deviation of the first code transition (00 . . . 000 to

00 . . . 001) from the ideal 1 LSB.

Negative Full-Scale Error (AD7893-10)

This is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal –4 ´ REF IN + 1 LSB (AD7893-10

± 10 V range) after Bipolar Zero Error has been adjusted out.

Negative Full-Scale Error (AD7893-3)

This is the deviation of the first code transition (10 . . . 000 to

10 . . . 001) from the ideal (–REF IN + 1 LSB) after Bipolar

Zero Error has been adjusted out.

Track/Hold Acquisition Time

Track/Hold acquisition time is the time required for the output

of the track/hold amplifier to reach its final value, within

± 1/2 LSB, after the end of conversion (the point at which the

track/hold returns to track mode). It also applies to situations

where there is a step input change on the input voltage applied

to the V IN input of the AD7893. This means that the user must

wait for the duration of the track/hold acquisition time after the

end of conversion or after a step input change to V IN before

starting another conversion, to ensure that the part operates to

specification.

THD ( dB ) = 20 log

V 2

+ V 2

V 1

where V 1 is the rms amplitude of the fundamental and V 2 , V 3 ,

V 4 , V 5 and V 6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f S /2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for parts

where the harmonics are buried in the noise floor, it will be a

noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for

which neither m nor n are equal to zero. For example, the second

order terms include (fa + fb) and (fa – fb), while the third order

terms include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).

The AD7893 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second and third order terms are of differ-

ent significance. The second order terms are usually distanced

in frequency from the original sine waves, while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified sepa-

rately. The calculation of the intermodulation distortion is per

the THD specification where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the fun-

damental expressed in dBs.

REV. E

–5–

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