ad667.pdf

Microprocessor-Compatible

12-Bit D/A Converter

AD667*

FEATURES

Complete 12-Bit D/A Function

Double-Buffered Latch

On Chip Output Amplifier

High Stability Buried Zener Reference

Single Chip Construction

Monotonicity Guaranteed Over Temperature

Linearity Guaranteed Over Temperature: 1/2 LSB max

Settling Time: 3

FUNCTIONAL BLOCK DIAGRAM

s max to 0.01%

Guaranteed for Operation with

12 V or

15 V

Supplies

Low Power: 300 mW Including Reference

TTL/5 V CMOS Compatible Logic Inputs

Low Logic Input Currents

MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD667 is a complete voltage output 12-bit digital-to-analog

converter including a high stability buried Zener voltage refer-

ence and double-buffered input latch on a single chip. The

converter uses 12 precision high speed bipolar current steering

switches and a laser trimmed thin-film resistor network to pro-

vide fast settling time and high accuracy.

Microprocessor compatibility is achieved by the on-chip double-

buffered latch. The design of the input latch allows direct inter-

face to 4-, 8-, 12-, or 16-bit buses. The 12 bits of data from the

first rank of latches can then be transferred to the second rank,

avoiding generation of spurious analog output values. The latch

responds to strobe pulses as short as 100 ns, allowing use with

the fastest available microprocessors.

The functional completeness and high performance in the

AD667 results from a combination of advanced switch design,

high speed bipolar manufacturing process, and the proven laser

wafer-trimming (LWT) technology. The AD667 is trimmed at

the wafer level and is specified to

C tem-

perature range and are available in a 28-pin molded plastic DIP

(N) or PLCC (P) package. The AD667S grade is specified for

the –55

C to +70

C range and is available in the ceramic DIP

(D) or LCC (E) package. The AD667A and B are specified for

use over the –25

C to +125

C temperature range and are avail-

able in a 28-pin hermetically sealed ceramic DIP (D) package.

C to +85

1% maximum error. The reference voltage is

also available for external application.

4. The gain setting and bipolar offset resistors are matched to

the internal ladder network to guarantee a low gain tempera-

ture coefficient and are laser-trimmed for minimum full-scale

and bipolar offset errors.

5. The precision high speed current steering switch and on-board

high speed output amplifier settle within 1/2 LSB for a 10 V

full-scale transition in 2.0

1/4 LSB maximum linearity

error (K, B grades) at +25

C and

1/2 LSB over the full operat-

ing temperature range.

The subsurface (buried) Zener diode on the chip provides a low

noise voltage reference which has long-term stability and tem-

perature drift characteristics comparable to the best discrete ref-

erence diodes. The laser trimming process which provides the

excellent linearity, is also used to trim the absolute value of the

reference as well as its temperature coefficient. The AD667 is

thus well suited for wide temperature range performance with

s as when properly compensated.

6. The AD667 is available in versions compliant with MIL-

STD-883. Refer to the Analog Devices Military Products

Databook or current AD667/883B data sheet for detailed

specifications.

1/2 LSB maximum linearity error and guaranteed monotonic-

ity over the full temperature range. Typical full-scale gain TC is

5 ppm/

* Protected by Patent Numbers 3,803,590; 3,890,611; 3,932,863; 3,978,473;

4,020,486; and others pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

The AD667 is available in five performance grades. The

AD667J and K are specified for use over the 0

PRODUCT HIGHLIGHTS

1. The AD667 is a complete voltage output DAC with voltage

reference and digital latches on a single IC chip.

2. The double-buffered latch structure permits direct interface

to 4-, 8-, 12-, or 16-bit data buses. All logic inputs are TTL

or 5 volt CMOS compatible.

3. The internal buried Zener reference is laser-trimmed to 10.00

volts with a

AD667–SPECIFICATIONS

(@ T A = +25 8 C, 6 12 V, 6 15 V power supplies unless otherwise noted)

Model

AD667J

AD667K

Min

Typ

Max

Min

Typ

Max

Units

DIGITAL INPUTS

Resolution

Bits

Logic Levels (TTL, Compatible, T MIN –T MAX ) 1

V IH (Logic “l’’)

+2.0

+5.5

+2.0

+5.5

V IL (Logic “0”)

+0.8

I IH (V IH = 5.5 V)

I IL (V IL = 0.8 V)

TRANSFER CHARACTERISTICS

ACCURACY

Linearity Error @ +25

+1/4

6 1/2

1/8

6 1/4

LSB

T A = T MIN to T MAX

1/2

6 3/4

1/4

6 1/2

LSB

Differential Linearity Error @ +25

1/2

6 3/4

1/4

6 1/2

LSB

T A = T MIN to T MAX

Monotonicity Guaranteed

LSB

Gain Error 2

0.1

6 0.2

0.1

6 0.2

% FSR 3

Unipolar Offset Error 2

6 2

LSB

Bipolar Zero 2

0.05

6 0.1

0.05

6 0.1

% of FSR

DRIFT

Differential Linearity

ppm of FSR/

Gain (Full Scale) T A = 25

C to T MIN or T MAX

ppm of FSR/

Unipolar Offset T A = –25

C to T MIN or T MAX

ppm of FSR/

Bipolar Zero T A = 25

C to T MIN or T MAX

ppm of FSR/

CONVERSION SPEED

Settling Time to

0.01% of FSR for

FSR Change (2 k

W i

500 pF Load)

with 10 k

Feedback

with 5 k

Feedback

For LSB Change

Slew Rate

ANALOG OUTPUT

Ranges 4

2.5,

10,

2.5,

10,

+5, +10

Output Current

Output Impedance (DC)

0.05

Short Circuit Current

REFERENCE OUTPUT

9.90

10.00

10.10

9.90

10.00

10.10

External Current

0.1

1.0

0.1

1.0

POWER SUPPLY SENSITIVITY

V CC = +11.4 V to +16.5 V dc

ppm of FS/%

V EE = –11.4 V to –16.5 V dc

ppm of FS/%

POWER SUPPLY REQUIREMENTS

Rated Voltages

± 12, ± 15

Range 4

6 11.4

6 16.5

6 11.4

6 16.5

Supply Current

+11.4 V to +16.5 V dc

–11.4 V to –16.5 V dc

TEMPERATURE RANGE

Specification

+70

°C

Storage

–65

+125

–65

+125

°C

NOTES

1 The digital input specifications are 100% tested at +25°C, and guaranteed but not tested over the full temperature range.

2 Adjustable to zero.

3 FSR means “Full-Scale Range” and is 20 V for ± 10 V range and 10 V for the ± 5 V range.

4 A minimum power supply of ± 12.5 V is required for a ± 10 V full-scale output and ± 11.4 V is required for all other voltage ranges.

Specifications subject to change without notice.

Specifications shown in boldface are tested on all production units at final electrical

test. Results from those tests are used to calculate outgoing quality levels. All min and

max specifications are guaranteed, although only those shown in boldface are tested

on all production units.

ABSOLUTE MAXIMUM RATINGS

V CC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V

V EE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V

Digital Inputs (Pins 11–15, 17–28)

to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V

Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ± 12 V

Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ± 12 V

10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 12 V

20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 24 V

Ref Out, V OUT (Pins 6, 9) . . Indefinite Short to Power Ground

. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V CC

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

C, V CC = +12 V or +15 V, V EE = –12 V or –15 V)

Symbol Parameter

Min Typ Max

t DC

Data Valid to End of CS

–

t AC

Ad d ress Valid to End of CS

100

t CP

CS Pulse Width

100

–

t DH

Data Hold Time

–

t SETT

Output Voltage Settling Time

–

–2–

REV. A

TIMING SPECIFICATIONS

(All Models, T A = +25

AD667

Model

AD667A

AD667B

AD667S

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Units

DIGITAL INPUTS

Resolution

Bits

Logic Levels (TTL, Compatible, T MIN –T MAX ) 1

V IH (Logic “l’’)

+2.0

+5.5

+2.0

+5.5

+2.0

+5.5

V IL (Logic “0”)

+0.8

+0.7

I IH (V IH = 5.5 V)

I IL (V IL = 0.8 V)

TRANSFER CHARACTERISTICS

ACCURACY

Linearity Error @ +25°C

+1/4

6 1/2

± 1/8

6 1/4

± 1/8

6 1/2

LSB

T A = T MIN to T MAX

± 1/2

6 3/4

± 1/4

6 1/2

± 1/8

6 3/4

LSB

Differential Linearity Error @ +25°C

± 1/2

6 3/4

± 1/4

6 1/2

± 1/4

6 3/4

LSB

T A = T MIN to T MAX

Monotonicity Guaranteed Monotonicity Guaranteed

Monotonicity Guaranteed

LSB

Gain Error 2

± 0.1

6 0.2

± 0.1

6 0.2

± 0.1

6 0.2

% FSR 3

Unipolar Offset Error 2

± 1

6 2

± 1

6 2

± 1

6 2

LSB

Bipolar Zero 2

± 0.05

6 0.1

± 0.05

6 0.1

± 0.05

6 0.1

% of FSR

DRIFT

Differential Linearity

± 2

ppm of FSR/°C

Gain (Full Scale) T A = 25°C to T MIN or T MAX

± 5

± 30

± 5

± 15

6 30

ppm of FSR/°C

Unipolar Offset T A = 25°C to T MIN or T MAX

± 1

± 3

6 3

ppm of FSR/°C

Bipolar Zero T A = 25°C to T MIN or T MAX

± 5

± 10

6 10

ppm of FSR/°C

CONVERSION SPEED

Settling Time to ± 0.01% of FSR for

FSR Change (2 kW i 500 pF Load)

with 10 kW Feedback

with 5 kW Feedback

For LSB Change

Slew Rate

V/ms

ANALOG OUTPUT

Ranges 4

± 2.5, ± 5, ± 10,

+5, +10

Output Current

± 5

Output Impedance (DC)

0.05

Short Circuit Current

REFERENCE OUTPUT

9.90

10.00

10.10

9.90

10.00

10.10

9.90

10.00 10.10

External Current

0.1

1.0

0.1

1.0

POWER SUPPLY SENSITIVITY

V CC = +11.4 V to +16.5 V dc

ppm of FS/%

V EE = –11.4 V to –16.5 V dc

ppm of FS/%

POWER SUPPLY REQUIREMENTS

Rated Voltages

12,

Range 4

6 11.4

6 16.5

6 11.4

6 16.5

6 11.4

6 16.5

Supply Current

+11.4 V to +16.5 V dc

–11.4 V to –16.5 V dc

TEMPERATURE RANGE

Specification

–25

+85

–25

+85

–55

+125

Storage

–65

+150

–65

+150

–65

+150

°C

TIMING DIAGRAMS

WRITE CYCLE #1

(Load First Rank from Data Bus; A3 = 1)

WRITE CYCLE #2

(Load Second Rank from First Rank; A2, A1, A0 = 1)

REV. A

–3–

AD667

PIN CONNECTIONS

PLCC, LCC

DIP

ORDERING GUIDE

from the ideal analog output (a straight line drawn from 0 to FS

– 1 LSB) for any bit combination. The AD667 is laser trimmed

to 1/4 LSB (0.006% of FS) maximum error at +25°C for the K

and B versions and 1/2 LSB for the J, A and S versions.

MONOTONICITY: A DAC is said to be monotonic if the

output either increases or remains constant for increasing digital

inputs such that the output will always be a nondecreasing func-

tion of input. All versions of the AD667 are monotonic over

their full operating temperature range.

DIFFERENTIAL NONLINEARITY: Monotonic behavior re-

quires that the differential linearity error be less than 1 LSB

both at +25°C and over the temperature range of interest. Dif-

ferential nonlinearity is the measure of the variation in analog

value, normalized to full scale, associated with a 1 LSB change

in digital input code. For example, for a 10 volt full-scale out-

put, a change of 1 LSB in digital input code should result in a

2.44 mV change in the analog output (1 LSB = 10 V ´ 1/4096 =

2.44 mV). If in actual use, however, a 1 LSB change in the

input code results in a change of only 0.61 mV (1/4 LSB) in

analog output, the differential linearity error would be –1.83 mV,

or –3/4 LSB. The AD667K and B grades have a max differential

linearity error of 1/2 LSB, which specifies that every step will be

at least 1/2 LSB and at most 1 1/2 LSB.

Linearity Gain

Temperature Error Max TC Max

Model l

Range— 8 C

@ +25 8 C

ppm/ 8 C Package Option 2

AD667JN

0 to +70

± 1/2 LSB 30

Plastic DIP (N-28)

AD667JP

0 to +70

± 1/2 LSB 30

PLCC (P-28A)

AD667KN

0 to +70

± 1/4 LSB 15

Plastic DIP (N-28)

AD667KP

0 to +70

± 1/4 LSB 15

PLCC (P-28A)

AD667AD

25 to +85

± 1/2 LSB 30

Ceramic DIP (D-28)

AD667BD

–25 to +85

± 1/4 LSB 15

Ceramic DIP (D-28)

AD667SD

–55 to +125

± 1/2 LSB 30

Ceramic DIP (D-28)

AD667SE

–55 to +125

± 1/2 LSB 30

LCC (E-28A)

AD667/883B –55 to +125

NOTES

*Refer to AD667/883B military data sheet.

1 For details on grade and package offerings screened in accordance with MIL-STD-

883, refer to the Analog Devices Military Products Databook or current AD667/

883B data sheet.

2 D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP;

P = Plastic Leaded Chip.

THE AD667 OFFERS TRUE 12-BIT PERFORMANCE

OVER THE FULL TEMPERATURE RANGE

LINEARITY ERROR: Analog Devices defines linearity error as

the maximum deviation of the actual, adjusted DAC output

Table I. Output Voltage Range Connections

Output

Digital

Connect

Range

Input Codes

Pin 9 to

Pin 1 to

Pin 2 to

Pin 4 to

10 V

Offset Binary

6 (Through 50

Fixed or 100

Trim Resistor)

± 5 V

Offset Binary

1 and 2

2 and 9

1 and 9

6 (Through 50 W Fixed or 100 W Trim Resistor)

± 2.5 V

Offset Binary

6 (Through 50 W Fixed or 100 W Trim Resistor)

0 V to +10 V

Straight Binary

1 and 2

2 and 9

1 and 9

5 (or Optional Trim—See Figure 2)

0 V to +5 V

Straight Binary

5 (or Optional Trim—See Figure 2)

–4–

REV. A

AD667

ANALOG CIRCUIT CONNECTIONS

Internal scaling resistors provided in the AD667 may be connected

to produce bipolar output voltage ranges of ± 10, ± 5 or ± 2.5 V or

unipolar output voltage ranges of 0 V to +5 V or 0 V to +10 V.

Gain and offset drift are minimized in the AD667 because of the

thermal tracking of the scaling resistors with other device com-

ponents. Connections for various output voltage ranges are

shown in Table I.

Figure 3. ± 5 V Bipolar Voltage Output

Figure 1. Output Amplifier Voltage Range Scaling Circuit

INTERNAL/EXTERNAL REFERENCE USE

The AD667 has an internal low noise buried Zener diode refer-

ence which is trimmed for absolute accuracy and temperature

coefficient. This reference is buffered and optimized for use in a

high speed DAC and will give long-term stability equal or superior

to the best discrete Zener reference diodes. The performance of

the AD667 is specified with the internal reference driving the

DAC since all trimming and testing (especially for full-scale

error and bipolar offset) is done in this configuration.

The internal reference has sufficient buffering to drive external

circuitry in addition to the reference currents required for the

DAC (typically 0. 5 mA to Ref In and 1.0 mA to Bipolar Off-

set). A minimum of 0.1 mA is available for driving external

loads. The AD667 reference output should be buffered with an

external op amp if it is required to supply more than 0.1 mA

output current. The reference is typically trimmed to

UNIPOLAR CONFIGURATION (Figure 2)

This configuration will provide a unipolar 0 volt to +10 volt out-

put range. In this mode, the bipolar offset terminal, Pin 4, should

be grounded if not used for trimming.

0.2%,

then tested and guaranteed to ± 1.0% max error. The tempera-

ture coefficient is comparable to that of the full-scale TC for a

particular grade.

If an external reference is used (10.000 V, for example), addi-

tional trim range must be provided, since the internal reference

has a tolerance of ± 1%, and the AD667 full-scale and bipolar

offset are both trimmed with the internal reference. The gain

and offset trim resistors give about

0.25% adjustment range,

which is sufficient for the AD667 when used with the internal

reference.

It is also possible to use external references other than 10 volts.

The recommended range of reference voltage is from +8 to

+11 volts, which allows both 8.192 V and 10.24 V ranges to be

used. The AD667 is optimized for fixed-reference applications.

If the reference voltage is expected to vary over a wide range in a

particular application, a CMOS multiplying DAC is a better

choice.

Reduced values of reference voltage will also permit the

Figure 2. 0 V to +10 V Unipolar Voltage Output

STEP I . . . ZERO ADJUST

Turn all bits OFF and adjust zero trimmer R1, until the output

reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is

not needed, and Pin 4 should be connected to Pin 5.

STEP II . . . GAIN ADJUST

Turn all bits ON and adjust 100 W gain trimmer R2, until the

output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than

nominal full scale of 10.000 volts.)

BIPOLAR CONFIGURATION (Figure 3)

This configuration will provide a bipolar output voltage from

–5.000 to +4.9976 volts, with positive full scale occurring with

all bits ON (all 1s).

STEP I . . . OFFSET ADJUST

Turn OFF all bits. Adjust 100 W trimmer R1 to give –5.000

volts output.

STEP II . . . GAIN ADJUST

Turn ON all bits. Adjust 100 W gain trimmer R2 to give a read-

ing of +4.9976 volts.

volt

5% power supply requirement to be relaxed to

12 volts

± 10%.

It is not recommended that the AD667 be used with external

feedback resistors to modify the scale factor. The internal resis-

tors are trimmed to ratio-match and temperature-track the other

resistors on the chip, even though their absolute tolerances are

20%, and absolute temperature coefficients are approximately

–50 ppm/

C. If external resistors are used, a wide trim range

(± 20%) will be needed and temperature drift will be increased

to reflect the mismatch between the temperature coefficients of

the internal and external resistors.

REV. A

–5–

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