EMIF02-MIC02F2.pdf

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356213021 UNPDF
®
EMIF02-MIC02F2
IPAD™
2 LINES EMI FILTER
INCLUDING ESD PROTECTION
MAIN PRODUCT CHARACTERISTICS:
Where EMI filtering in ESD sensitive equipment is
required:
■ Mobile phones and communication systems
■ Computers, printers and MCU Boards
DESCRIPTION
The EMIF02-MIC02 is a highly integrated devices
designed to suppress EMI/RFI noise in all systems
subjected to electromagnetic interferences. The
EMIF02 flip chip packaging means the package
size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
■
Flip-Chip
(6 Bumps)
Table 1: Order Code
Part Number
Marking
EMI symmetrical (I/O) low-pass filter
EMIF02-MIC02F2
FJ
High efficiency in EMI filtering
■
Lead free package
■
Very low PCB space consuming:
1.07mm x 1.57mm
■
Figure 1: Pin Configuration (Ball side)
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
High reliability offered by monolithic integration
■
High reducing of parasitic elements through
integration & wafer level packaging.
3
2
1
■
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4 on input pins 15kV (air discharge)
8kV (contact discharge)
I2
GND
I1
A
O2
GND
O1
B
Level 1 on output pins 2kV (air discharge)
2kV (contact discharge)
Figure 2: Basic Cell Configuration
Low-pass Filter
Input
Output
Cline = 16p Ω
GND
GND
GND
TM: IPAD is a trademark of STMicroelectronics.
October 2004
REV. 1
1/7
Ri/o = 470
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EMIF02-MIC02F2
Table 2: Absolute Ratings (limiting values)
Symbol
Parameter and test conditions
Value
Unit
T j
Maximum junction temperature
125
°C
T op
Operating temperature range
- 40 to + 85
°C
T stg
Storage temperature range
- 55 to + 150
°C
Table 3: Electrical Characteristics (T amb = 25°C)
Symbol Parameter
V BR Breakdown voltage
I RM Leakage current @ V RM
V RM Stand-off voltage
V CL Clamping voltage
R d Dynamic impedance
I PP Peak pulse current
R I/O Series resistance between Input &
Output
C line Input capacitance per line
I
I PP
V CL
V BR
V RM
I R
I RM
V
I RM
I R
V RM
V BR
V CL
I PP
Symbol
Test conditions
Min.
Typ.
Max.
Unit
V BR
I R = 1 mA
14
16
V
I RM
V RM = 12V per line
500
nA
R I/O
423
470
517
Ω
C line
@ 0V
16
pF
Figure 3: S21 (dB) attenuation measurement
and Aplac simulation
Figure 4: Analog crosstalk measurements
- 10.00
dB
dB
-20.00
dB
- 15.00
-30.00
- 20.00
Measurement
-40.00
I2/O1
- 25.00
- 30.00
-50.00
- 35.00
-60.00
- 40.00
- 45.00
-70.00
Simulation
- 50.00
-80.00
1.0M
3.0M
10.0M 30.0M
100.0M 300.0M
1.0G
3.0G
1.0M
3.0M
10.0M
30.0M
100.0M 300.0M
1.0G
3.0G
f/Hz
f/Hz
2/7
-
-
-
-
-
-
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EMIF02-MIC02F2
Figure 5:Digitalcrosstalkmeasurement
Figure 6: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 7: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 8: Line capacitance versus applied
voltage
C(pF)
20
18
F=1MHz
V osc =30mV RMS
T j =25°C
16
14
12
10
8
6
4
2
V (V)
R
0
0123456789012
3/7
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EMIF02-MIC02F2
Figure 9: Aplac model
I1
R_470R
O1
gnd
Cox
MODEL = D01-int
Cox
50pH
MODEL = D01-ext
50pH
Rsubump
Rsubump
50m
50m
MODEL = D01-gnd
gnd
Rsubump
Rsubump
Lgnd
Lgnd
Cgnd
MODEL = D01-ext
Cgnd
Cox
MODEL = D01-int
Cox
Rgnd
Rgnd
I2
O2
R_470R
Figure 10: Aplac parameters
Model D01-ext
BV = 7
CJO = Cz_ext
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N = 1
M = 0.3333
RS = Rs_ext
VJ = 0.6
TT = 50n
Model D01-int
BV = 7
CJO = Cz_int
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N = 1
M = 0.3333
RS = Rs_int
VJ = 0.6
TT = 50n
Model D01-gnd
BV = 7
CJO = Cz_gnd
IBV = 1u
IKF = 1000
IS = 10f
ISR = 100p
N = 1
M = 0.3333
RS = Rs_gnd
VJ = 0.6
TT = 50n
Ls 400pH
Rs 100m
R_470R 482.6
Cz_ext 8.73pF
Rs_ext 850m
Cz_int 2.9pF
Rs_int 850m
Cz_gnd 215.61pF
Rs_gnd 470m
Rgnd 10m
Lgnd 48pH
Cgnd 0.15pF
Cox 3.05pF
Rsubump 200m
4/7
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EMIF02-MIC02F2
Figure 11: Ordering Information Scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
= 3: Leadfree Pitch = 400µm, Bump = 250µm
Figure 12: FLIP-CHIP Package Mechanical Data
500µm ± 50
315µm ± 50
650µm ± 65
1.07mm ± 50µm
Figure 13: Foot print recommendations
Figure 14: Marking
Dot, ST logo
xx = marking
365
240
Copper pad Diameter :
250µm recommended , 300µm max
z = packaging
location
yww = datecode
(y = year
ww = week)
Solder stencil opening : 330µm
E
x
y
x
w
z
w
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
All dimensions in µm
5/7
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