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ADE7753 Single-Phase Multifunction Metering IC with di/dt Sensor Interface Data Sheet (REV. A)
Single-Phase Multifunction Metering IC
with di/dt Sensor Interface
ADE7753
FEATURES
High accuracy; supports IEC 60687/61036/61268 and
IEC 62053-21/62053-22/62053-23
On-chip digital integrator enables direct interface to current
sensors with di/dt output
Active, reactive, and apparent energy; sampled waveform;
current and voltage rms
Less than 0.1% error in active energy measurement over a
dynamic range of 1000 to 1 at 25°C
Positive-only energy accumulation mode available
On-chip user programmable threshold for line voltage surge
and SAG and PSU supervisory
Digital calibration for power, phase, and input offset
On-chip temperature sensor (±3°C typical)
SPI® compatible serial interface
Pulse output with pro gra mmable frequency
Interrupt request pin ( IRQ ) and status register
Reference 2.4 V with external overdrive capability
Single 5 V supply, low power (25 mW typical)
GENERAL DESCRIPTION
The ADE7753 features proprietary ADCs and DSP for high
accuracy over large variations in environmental conditions and
time. The ADE7753 incorporates two second-order 16-bit Σ-∆
ADCs, a digital integrator (on CH1), reference circuitry,
temperature sensor, and all the signal processing required to
perform active, reactive, and apparent energy measurements,
line-voltage period measurement, and rms calculation on the
voltage and current. The selectable on-chip digital integrator
provides direct interface to di/dt current sensors such as
Rogowski coils, eliminating the need for an external analog
integrator and resulting in excellent long-term stability and pre-
cise phase matching between the current and voltage channels.
The ADE7753 provides a serial interface to read data, and a
pulse output frequency (CF), which is proportional to the active
power. Various system calibration features, i.e., channel offset
correction, phase calibration, and power calibration, ensure high
accuracy. The part also detects short duration low or high
voltage variations.
The positive-only accumulation mode gives the option to
accumulate energy only when positive power is detected. An
internal no-load threshold ensures that the part does not exhibit
any creep when there is no load. The zero-crossing output (ZX)
produces a pulse that is synchronized to the zero-crossing point
of the line voltage. This signal is used internally in the line cycle
active and apparent energy accumulation modes, which enables
faster calibration.
The interrupt status register indicates the nature of the interrupt,
and the interrupt ena ble register controls which event produces
an output on the IRQ pin, an open-drain, active low logic output.
The ADE7753 is available in a 20-lead SSOP package.
FU NCT IONAL BLOCK DIAGRAM
AVDD
RESET
DVDD
DGND
PGA
INTEGRATOR
WGAIN[11:0]
ADE7753
MULTIPLIER
LPF2
V1P
V1N
ADC
dt
HPF1
CFNUM[11:0]
TEMP
SENSOR
APOS[15:0]
π
2
PHCAL[5:0]
DFC
CF
Φ
IRMSOS[11:0]
CFDEN[11:0]
x 2
VAGAIN[11:0]
PGA
VRMSOS[11:0]
V2P
ADC
x 2
V2N
VADIV[7:0]
% %
WDIV[7:0]
LPF1
ZX
2.4V
REFERENCE
4k
REGISTERS AND
SERIAL INTERFACE
SAG
AGND
REF IN/OUT
CLKIN CLKOUT
DIN DOUT SCLK
CS IRQ
02875-A-001
Figure 1.
*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
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ADE7753
REVISION HISTORY
6/04—Changed from Rev. 0 to Rev A
Changes IEC Standards ................................................................... 1
Changes to Phase Error Between Channels Definition............... 7
Changes to Figure 24...................................................................... 13
Changes to CH2OS Register ......................................................... 16
Change to the Period Measurement Section............................... 18
Change to Temperature Measurement Section .......................... 21
Changes to Figure 69...................................................................... 31
Changes to Figure 71...................................................................... 33
Changes to the Apparent Energy Section.................................... 36
Changes to Energies Scaling Section ........................................... 37
Changes to Calibration Section .................................................... 37
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 60
423471194.005.png
ADE7753
SPECIFICATIONS
AV DD = DV DD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T MIN to T MAX = –40°C to +85°C.
Table 1.
Parameter 1
Spec
Unit
Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Active Power Measurement Error
CLKIN = 3.579545 MHz
Channel 1 Range = 0.5 V Full Scale
Channel 2 = 300 mV rms/60 Hz, gain = 2
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.1
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.25 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.125 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.2
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Active Power Measurement Bandwidth
14
kHz
Phase Error 1 between Channels 2
±0.05
max
Line Frequency = 45 Hz to 65 Hz, HPF on
AC Power Supply Rejection 2
AV DD = DV DD = 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF)
0.2
% typ
Channel 1 = 20 mV rms, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
DC Power Supply Rejection 2
AV DD = DV DD = 5 V ± 250 mV dc
Output Frequency Variation (CF)
±0.3
% typ
Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
IRMS Measurement Error
0.5
% typ
Over a dynamic range 100 to 1
IRMS Measurement Bandwidth
14
kHz
VRMS Measurement Error
0.5
% typ
Over a dynamic range 20 to 1
VRMS Measurement Bandwidth
140
Hz
ANALOG INPUTS 3
See the Analog Inputs s ection
Maximum Signal Levels
±0.5
V max
V1P, V1N, V2N, and V2P to AGND
Input Impedance (dc)
390
k min
Bandwidth
14
kHz
CLKIN/256, CLKIN = 3.579545 MHz
Gain Error 2, 3
External 2.5 V reference, gain = 1 on Channels 1 and 2
Channel 1
Range = 0.5 V Full Scale
±4
% typ
V1 = 0.5 V dc
Range = 0.25 V Full Scale
±4
% typ
V1 = 0.25 V dc
Range = 0.125 V Full Scale
±4
% typ
V1 = 0.125 V dc
Channel 2
±4
% typ
V2 = 0.5 V dc
Offset Error 2
±32
mV max
Gain 1
Channel 1
±13
mV max
Gain 16
±32
mV max
Gain 1
Channel 2
±13
mV max
Gain 16
WAVEFORM SAMPLING
Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
Channel 1
See the Channel 1 Sampling s ection
Signal-to-Noise Plus Distortion
62
dB typ
150 mV rms/60 Hz, range = 0.5 V, gain = 2
Bandwidth(–3 dB)
14
kHz
CLKIN = 3.579545 MHz
Footnotes on next page.
Rev. A | Page 3 of 60
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ADE7753
Parameter
Spec
Unit
Test Conditions/Comments
Channel 2
See the Channel 2 Sampling s ection
Signal-to-Noise Plus Distortion
60
dB typ
150 mV rms/60 Hz, gain = 2
Bandwidth (–3 dB)
140
Hz
CLKIN = 3.579545 MHz
REFERENCE INPUT
REF IN/OUT Input Voltage Range
2.6
V max
2.4 V + 8%
2.2
V min
2.4 V – 8%
Input Capacitance
10
pF max
ON-CHIP REFERENCE
Nominal 2.4 V at REF IN/OUT pin
Reference Error
±200
mV max
Current Source
10
µA max
Output Impedance
3.4
kΩ min
Temperature Coefficient
30
ppm/°C typ
CLKIN
All specifications CLKIN of 3.579545 MHz
Input Clock Frequency
4
MHz max
1
MHz min
LO GIC IN PUTS
RESET , DIN, SCLK, CLKIN, and CS
Input High Voltage, V INH
2.4
V min
DV DD = 5 V ± 10%
Input Low Voltage, V INL
0.8
V max
DV DD = 5 V ± 10%
Input Current, I IN
±3
µA max
Typically 10 nA, V IN = 0 V to DV DD
Input Capacitance, C IN
10
pF max
LO GIC OUT PUT S
SAG and IRQ
Open-drain outputs, 10 kΩ pull-up resistor
Output High Voltage, V OH
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
0.4
V max
I SINK = 0.8 mA
ZX and DOUT
Output High Voltage, V OH
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
0.4
V max
I SINK = 0.8 mA
CF
Output High Voltage, V OH
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
1
V max
I SINK = 7 mA
POWER SUPPLY
For specified performance
AVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
DVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
AI DD
3
mA max
Typically 2.0 mA
DI DD
4
mA max
Typically 3.0 mA
_______________________________________________
1 See the plots in the Typical Performance Characteristics s ection.
2 See the Terminology s ection for explanation of specifications.
3 See the Analog Inputs s ection.
200 µ A
I Ol
TO
OUTPUT
PIN
C L
50pF
+2.1V
1.6mA
I OH
02875-0-002
Figure 2. Load Circuit for Timing Specifications
Rev. A | Page 4 of 60
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ADE7753
TIMING CHARACTERISTICS
AV DD = DV = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T
DD
MIN to T MAX = –40°C to +85°C.
Table 2.
Parameter 1, 2
Spec
Unit
Test Conditions/Comments
Write Timing
t 1
50
ns (min)
CS falling edge to first SCLK falling edge.
t 2
50
ns (min)
SCLK logic high pulse width.
t 3
50
ns (min)
SCLK logic low pulse width.
t 4
10
ns (min)
Valid data setup time before falling edge of SCLK.
t 5
5
ns (min)
Data hold time after SCLK falling edge.
t 6
400
ns (min)
Minimum time between the end of data byte transfers.
t 7
50
ns (min)
Mi nimum time between byte transfers during a serial write.
t 8
100
ns (min)
CS hold time after SCLK falling edge.
Read Timing
t 9 3
4
µs (min)
Minimum time between read command (i.e., a write to
communication register) and data read.
t 10
50
ns (min)
Minimum time between data byte transfers during a multibyte read.
t 11
30
ns (min)
Data access time after SCLK rising edge following a write to the
communications register.
t 12 4
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t 13 5
100
ns (max)
Bus relinquish time after rising edge of CS .
10
ns (min)
___________________________________
1 Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
3 Minimum time between read command and data read for all registers except waveform register, which is t 9 = 500 ns min.
4 Measured with the load circuit in Figure 2 a nd defined as the time required for the output to cross 0.8 V or 2.4 V.
5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t 8
CS
t 1
t 3
t 6
SCLK
t 7
t 7
t 2
t 4
t 5
DIN
1
0
A5
A4
A3
A2
A1
A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 3. Serial Write Timing
CS
t 1
t 13
SCLK
t 9
t 10
DIN
0
0
A5
A4
A3
A2
A1
A0
t 11
t 11
t 12
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 4. Serial Read Timing
Rev. A | Page 5 of 60
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