TP3406.PDF

November 1992

TP3406

DASL Digital Adapter for Subscriber Loops

General Description

The TP3406 is a complete monolithic transceiver for data

transmission on twisted pair subscriber loops. It is built on

National's double poly microCMOS process, and requires

only a single a 5 Volt supply. Alternate Mark Inversion (AMI)

line coding, in which binary `1's are alternately transmitted

as a positive pulse then a negative pulse, is used to ensure

low error rates in the presence of noise with lower emi radia-

tion than other codes such as Bi-phase (Manchester).

Full-duplex transmission at 144 kb/s is achieved on a single

twisted wire pair using a burst-mode technique (Time Com-

pression Multiplexed). Thus the device operates as an ISDN

`U' Interface for short loop applications, typically in a PBX

environment, providing transmission for 2 B channels and 1

D channel. On Ý 24 cable, the range is up to 800 meters.

System timing is based on a Master/Slave configuration,

with the line card end being the Master which controls loop

timing and synchronisation. All timing sequences necessary

for loop activation and de-activation are generated on-chip.

Selection of Master and Slave mode operation is pro-

grammed via the Microwire Control Interface.

A 2.048 MHz clock, which may be synchronized to the sys-

tem clock, controls all transmission-related timing functions.

Features

Complete ISDN PBX 2-Wire Data Transceiver including:

Y 2 B plus D channel interface for PBX U Ê Interface

Y 144 kb/s full-duplex on 1 twisted pair using Burst Mode

Y Loop range up to 800 meters ( Ý 24AWG)

Y Alternate Mark Inversion coding with transmit filter and

scrambler for low emi radiation

Y Adaptive line equalizer

Y On-chip timing recovery, no external components

Y Standard TDM interface for B channels

Y Separate interface for D channel

Y 2.048 MHz master clock

Y Driver for line transformer

Y 4 loop-back test modes

Y Single a 5V supply

Y MICROWIRE TM compatible serial control interface

Y Applications in:

PBX Line Cards

Terminals

Regenerators

Y Available in 28-pin PLCC Package

Block Diagram

TL/H/11725±1

TRI-STATE É is a registered trademark of National Semiconductor Corporation

MICROWIRE TM is a trademark of National Semiconductor Corporation.

C 1995 National Semiconductor Corporation

TL/H/11725

RRD-B30M115/Printed in U. S. A.

Connection Diagram

TP3406 Package Information

TL/H/11725±2

Order Number TP3406V

See NS Package Number V28A

Pin Descriptions

Name Description

GND Negative power supply pin, normally 0V. All

analog and digital signals are referred to this

pin.

V CC Positive power supply input, which must be

a 5V g 5%.

MCLK The 2.048 MHz Master Clock input, which

requires a CMOS logic level clock input from

a stable source. Must be synchronous with

BCLK.

MCLK/XTAL This pin is the 2.048 MHz Master Clock in-

put, which requires either a crystal to be con-

nected between this pin and XTAL2 or a

CMOS logic level clock from a stable source,

which must be synchronous with BCLK.

XTAL2 This pin is the output side of the oscillator

amplifier.

MBS/FS C In Master Mode, this pin is the Master Burst

Sync input, which may be clocked at 4 kHz

to synchronize Transmit bursts from a num-

ber of devices at the Master end only. The 4

kHz should be nominally a square wave sig-

nal. If not used leave this pin open. In Slave

mode, this pin is a short Frame Sync output,

suitable for driving another DASL in Master

Mode to provide a regenerator (i.e. range-ex-

tender) capability.

Name Description

tal output pulse which indicates the 8-bit pe-

riods of the B1 channel data transfer at both

B x and B r .

FS b In Master mode only, this pin is the Receive

Frame Sync pulse input, requiring a positive

edge to indicate the start of the active chan-

nel time of the device for receive B channel

data out from B r ;FS b must be synchronous

with BCLK and MCLK. In Slave mode only,

this pin is a digital output pulse which indi-

cates the 8-bit periods of the B2 channel

data transfer at both B x and B r .

B x Digital input for B1 and B2 channel data to

be transmitted to the line; must be synchro-

nous with BCLK.

B r Digital output for B1 and B2 channel data

received from the line.

TS r /LSD In Master mode only, this pin is an open-

drain output which is normally high imped-

ance but pulls low during both B channel ac-

tive receive time slots. In Slave mode only,

this pin is an output which is normally high

impedance and pulls low when a valid line

signal is received.

D x Digital input for D channel data to be trans-

mitted to the line; must be synchronous with

DCLK.

D r Digital output for D channel data received

from the line. D r is a TRI-STATE output.

DCLK/DEN In Master mode this pin is an input for the

16 kHz serial shift clock for D channel data

on D x and D r , which should be synchronous

with BCLK. It may also be re-configured via

the Control Register to act as an enable in-

put for clocking the D channel interface syn-

chronized to BCLK. In Slave mode this is a

16 kHz clock output for D channel data.

*Crystal specifications: 2.048 MHz parallel resonant, R S s 100 X with a

20 pF load. Crystal tolerance should be g 75 ppm for aging and tempera-

ture.

BCLK

Bit Clock logic signal which determines the

data shift rate for B channel data on the digi-

tal interface side of the device. In Master

mode this pin is an input which may be any

multiple of 8 kHz from 256 kHz to

2.048 MHz, but must be synchronous with

MCLK. In Slave mode this pin is an output at

2.048 MHz.

FS a

In Master mode only, this pin is the Transmit

Frame Sync pulse input, requiring a positive

edge to indicate the start of the active chan-

nel time for transmit B channel data into B x ;

FS a must be synchronous with BCLK and

MCLK. In Slave mode only, this pin is a digi-

Pin Descriptions (Continued)

Name

Description

LINE TRANSMIT SECTION

Alternate Mark Inversion (AMI) line coding is used on the

DASL because of its spectral efficiency and null dc energy

content. All transmitted bits, excluding the start bit, are

scrambled by a 9-bit scrambler to provide good spectral

spreading with a strong timing content. The scrambler feed-

back polynomial is:

MICROWIRE control channel serial data in-

put.

MICROWIRE control channel serial data out-

put.

CCLK

Clock input for the MICROWIRE control

channel.

x 9 a x 5 a 1.

Pulse shaping is obtained by means of a raised cosine

switched-capacitor filter, in order to limit rf energy and

crosstalk while minimizing inter-symbol interference (isi).

Figure3 shows the pulse shape at the L o output, while a

template for the typical power spectrum transmitted to the

line with random data is shown in Figure4.

The line-driver output, L o , is designed to drive a transformer

through a capacitor and termination resistor. A 1:1 trans-

former, terminated in 100 X , results in a signal amplitude of

typically 1.3V pk-pk on the line. Over-voltage protection

must be included in the interface circuit.

LINE RECEIVE SECTION

The front-end of the receive section consists of a continu-

ous anti-alias filter followed by a switched-capacitor low-

pass filter designed to limit the noise bandwidth with mini-

mum intersymbol interference. To correct pulse attenuation

and distortion caused by the transmission line an AGC cir-

cuit and first-order equalizer adapt to the received pulse

shape, thus restoring a ``flat'' channel response with maxi-

mum received eye opening over a wide spread of cable

attenuation characteristics.

From the equalized output a DPLL (Digital Phase-Locked

Loop) recovers a low-jitter clock for optimum sampling of

the received symbols. The MCLK input provides the refer-

ence clock for the DPLL at 2.048 MHz. At the Master end of

the loop this reference is the network clock (BCLK), which

controls all transmit functions; the DPLL clock is used only

for received data sampling. At the Slave end, however, a

2.048 MHz crystal is required to generate a stable local os-

cillator which is used as a reference by the DPLL to run both

the receive and transmit sides of the DASL device.

Following detection of the recovered symbols, the received

data is de-scrambled by the same x 9 a x 5 a 1 polynomial

and presented to the digital system interface circuit.

When the device is de-activated, a Line-Signal Detect circuit

remains powered-up to detect the presence of incoming

bursts if the far-end starts to activate the loop. From a

``cold'' start, acquisition of bit timing and equalizer conver-

gence with random scrambled data takes approximately

25 ms at each end of the loop. Full loop burst synchroniza-

tion is achieved approximately 50 ms after the ``activate''

command at the originating end.

Chip Select input which enables the MICRO-

WIRE control channel data to be shifted in

and out when pulled low. When high, this pin

inhibits the MICROWIRE interface.

INT

Interrupt output, a latched output signal

which is normally high-impedance and goes

low to indicate a change of status of the loop

transmission system. This latch is cleared

when the Status Register is read by the mi-

croprocessor.

L o

Transmit AMI signal output to the line trans-

former. This pin is capable of driving a load

impedance t 60 X .

L i

Receive AMI signal input from the line trans-

former. This is a high impedance input.

Functional Description

POWER-UP/POWER-DOWN CONTROL

Following the initial application of power, the DASL enters

the power-down (de-activated) state, in which all the internal

circuits are inactive and in a low power state except for the

line-signal detect circuit and the necessary bias circuit; the

line output L o is in a low impedance state and all digital

outputs are inactive. All bits in the Control Register power-

up initially set to `0', so that the device always initializes as

the Master end. Thus, at the Slave end, a control word must

be written through the MICROWIRE port to select Slave

mode. While powered-down, the Line-Signal Detect circuits

in both Master and Slave devices continually monitor the

line, to enable loop transmission to be initiated from either

end.

To power-up the device and initiate activation, bit C6 in the

Control Register must be set high. Setting C6 low de-acti-

vates the loop and powers-down the device, see Table I.

TABLE I. Master Mode Burst

Sync Control (TP3401 Only)

MBS/FS c

Pin I/P

Action

State

at Master

Don't Care 0 Powered-down, Line-Signal

Detect active

Pull up this pin 1 Powered-up, sending bursts

synchronized to FS a

to a 5V through

a resistor

4 kHz

1 Powered-up, sending bursts

synchronized to MBS

Functional Description (Continued)

TL/H/11725±3

FIGURE 3. Typical AMI Waveform at L o

TL/H/11725±4

FIGURE 4. Typical AMI Transmit Spectrum Measured at LO Output (With RBW e 100 Hz).

TL/H/11725±5

FIGURE 5. Burst Mode Timing on the Line

Functional Description (Continued)

BURST MODE OPERATION

For full-duplex operation over a single twisted-pair, burst

mode timing is used, with the line-card (exchange) end of

the link acting as the timing Master.

Each burst from the Master consists of the B1, B2 and D

channel data from 2 consecutive frames combined in the

format shown in Figure5. During transmit bursts the Mas-

ter's receiver input is inhibited to avoid disturbing the adap-

tive circuits. The Slave's receiver is enabled at this time and

it synchronizes to the start bit of the burst, which is always

an unscrambled `1' (of the opposite polarity to the last `1'

sent in the previous burst). When the Slave detects that 36

bits following the start bit have been received, it disables the

receiver input, waits 6 line symbol periods to match the oth-

er end settling guard time, and then begins to transmit its

burst back towards the Master, which by this time has en-

abled its receiver input. The burst repetition rate is thus

4 kHz, which can either free-run or be locked to a synchro-

nizing signal at the Master end by means of the MBS input

(See Figure 10). In the latter case, with all Master-end

transmitters in a system synchronized together, near-end

crosstalk between pairs in the same cable binder may be

eliminated, with a consequent increase in signal-to-noise ra-

tio (SNR).

ACTIVATION AND LOOP SYNCHRONIZATION

Activation (i.e. power-up and loop synchronization) is typi-

cally completed in 50 ms and may be initiated from either

end of the loop. If the Master is activating the loop, it sends

normal bursts of scrambled `1's, which are detected by the

Slave's line-signal detect circuit, cau sing it to set C0 e 1in

the Status Register, and pull the INT pin low. Pin 6, the LSD

pin, also pulls low. To proceed with Activation, the device

must be powered up by writing to the Control Register with

C6 e 1. The Slave then replies with bursts of scrambled

`1's synchronized to received bursts, and the flywheel circuit

at each end searches for 4 consecutive correctly formatted

receive bursts to acquire full loop synchronization. Each re-

ceiver indicates when it is correctly in sync with received

bursts by s etting the C1 bit in the Status Register high and

pulling INT low.

To activate the loop from the Slave end, bit C6 in the Con-

trol Register must be set high, which will power-up the de-

vice and begin transmission of alternate bursts i.e., the burst

repetition rate is 2 kHz, not 4 kHz. At this point the Slave is

running from its local oscillator and is not receiving any sync

information from the Master. When the Master's line-signal

detect circuit recognizes this ``wake-up'' signal, the Master

is activated and begins to transmit bursts, synchronized, as

normal, to the MBS or FS a input with a 4 kHz repetition rate.

This enables the Slave's receiver to correctly identify burst

timing from the Master and to re-synchronize its own burst

transmissions to those it receives. The flywheel circuits then

acquire full loop sync as described earlier.

Loop synchronization is considered to be lost if the flywheel

finds 4 consecutive receive burst ``windows'' (i.e. where a

receive burst should have arrived based on timing from pre-

vious bursts) do not contain valid burst s. A t this point bit C1

in the Status Register is set low, the INT output is set low

and the receiver searches to re-acquire loop sync.

DIGITAL SYSTEM INTERFACE

The digital system interface on the DASL separates B and D

channel information onto different pins to provide maximum

flexibility. On the B channel interface, phase skew between

transmit and receive directions may be accommodated at

the Master end since separate frame sync inputs, Fs a and

Fs b , are provided. Each of these synchronizes a counter

which gates the transfer of B1 and B2 channels in consecu-

tive time-slots across the digital interface; since the coun-

ters are edge-synchronized the duration of the F s input sig-

nals may vary from a single-bit pulse to a square-wave. The

serial shift rate is determined by the BCLK input, and may

be any frequency from 256 kHz to 2.048 MHz, as shown in

Figure6.

At the Slave end, both Fs a and Fs b are outputs. Fs a goes

high for 8 cycles of BCLK coincident with the 8 bits of the

B1 channel in both Transmit and Receive directions. Fs b

goes high for the next 8 cycles of BCLK, which are coinci-

dent with the 8 bits of the B2 channel in both Transmit and

Receive directions. BCLK is also an output at 2.048 MHz,

the serial data shift rate, as shown in Figure7. Data may be

exchanged between the B1 and B2 channels as it passes

through the device, by setting Control bit C0 e 1. An addi-

tional Frame Sync output, FS c , is provided to enable a re-

generator to be built by connecting a DASL in Slave Mode

to a DASL in Master Mode. The FS c output from the Slave

directly drives the FS a and FS b inputs on the Master.

D channel information, being packet-mode, requires no syn-

chronizing input. This interface consists of the transmit data

input, D x , receive data output, D r , and 16 kHz serial shift

clock DCLK, which is an input at the Master end and an

output at the Slave end. Data shifts into D x on falling edges

of DCLK and out from D r on rising edges, as shown in Fig-

ure11. DCLK should be Synchronous with BCLK.

An alternative function of the DCLK/DEN pin allows D x and

D r to be clocked at the same rate as BCLK at the Master

end only. By setting bit C1 in the Control Register to a 1,

DCLK/DEN becomes an input for an enabling pulse to gate

2 cycles of BCLK for shifting the 2 D bits per frame. Thus, at

the Master end, the D channel bits can be interfaced to a

TDM bus and assigned to a time-slot (the same time-slot for

both transmit and receive), as shown in Figure12.

CONTROL INTERFACE

A serial interface, which can be clocked independently from

the B and D channel system interfaces, is provided for mi-

croprocessor control of various functions on the DASL de-

vice. All data transfers consist of a single byte shifted into

the Control Register via CI simultaneous with a single byte

shifted out from the Status Register via CO, see Figure13.

Data shifts in to CI on risin g e dges of CCLK and out from

CO on falling edges when CS is pulled low for 8 cycles of

CCLK. An Interrupt output, INT goes low to alert the micro-

processor whenever a change in one of the status bits, C1

and/or C0 has occurred. This latche d ou tput is cleared high

following the first CCLK pulse when CS is low. No interrupt

is generated when status bit C2 (bipolar violation) goes high,

however. This bit is set whenever 1 or more violations of t he

AMI coding rule is received, and cleared everytime the CS is

pulsed. Statistics on the line bit error rate can be accumulat-

ed by regularly polling this bit.

When reading the CO pin, data is always clocked into the

Control Register; therefore the CI data word should repeat

the previous instruction if no change to the device mode is

intended.

Figure13 shows the timing for this interface, and Table II

lists the control functions and status indicators.

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: