TP3070 TP3071.PDF

April 1994

TP3070, TP3071, TP3070-X

COMBO É II Programmable PCM CODEC/Filter

General Description

The TP3070 and TP3071 are second-generation combined

PCM CODEC and Filter devices optimized for digital switch-

ing applications on subscriber line and trunk cards. Using

advanced switched capacitor techniques, COMBO II com-

bines transmit bandpass and receive lowpass channel filters

with a companding PCM encoder and decoder. The devices

are A-law and m -law selectable and employ a conventional

serial PCM interface capable of being clocked up to

4.096 MHz. A number of programmable functions may be

controlled via a serial control port.

Channel gains are programmable over a 25.4 dB range in

each direction, and a programmable filter is included to en-

able Hybrid Balancing to be adjusted to suit a wide range of

loop impedance conditions. Both transformer and active

SLIC interface circuits with real or complex termination im-

pedances can be balanced by this filter, with cancellation in

excess of 30 dB being readily achievable when measured

across the passband against standard test termination net-

works.

To enable COMBO II to interface to the SLIC control leads,

a number of programmable latches are included; each may

be configured as either an input or an output. The TP3070

provides 6 latches and the TP3071 5 latches.

See also AN-614, COMBO II application guide.

Features

Y Complete CODEC and FILTER system including:

Ð Transmit and receive PCM channel filters

Ð m -law or A-law companding encoder and decoder

Ð Receive power amplifier drives 300 X

Ð 4.096 MHz serial PCM data (max)

Y Programmable Functions:

Ð Transmit gain: 25.4 dB range, 0.1 dB steps

Ð Receive gain: 25.4 dB range, 0.1 dB steps

Ð Hybrid balance cancellation filter

Ð Time-slot assignment; up to 64 slots/frame

Ð 2 port assignment (TP3070)

Ð 6 interface latches (TP3070)

ÐAor m -law

Ð Analog loopback

Ð Digital loopback

Y Direct interface to solid-state SLICs

Y Simplifies transformer SLIC; single winding secondary

Y Standard serial control interface

Y 80 mW operating power (typ)

Y 1.5 mW standby power (typ)

Y Designed for CCITT and LSSGR applications

Y TTL and CMOS compatible digital interfaces

Y Extended temperature versions available for b 40 § Cto

a 85 § C (TP3070V-X)

Block Diagram

TL/H/8635±1

FIGURE 1

COMBO É and TRI-STATE É are registered trademarks of National Semiconductor Corporation.

C 1995 National Semiconductor Corporation

TL/H/8635

RRD-B30M115/Printed in U. S. A.

Connection Diagrams

TL/H/8635±2

TL/H/8635±4

Order Number TP3071J

See NS Package Number J20A

Order Number TP3071N

See NS Package Number N20A

Order Number TP3070V

(0 § Cto a 70 § C)

Order Number TP3070V-X

( b 40 § Cto a 85 § C)

See NS Package Number V28A

Pin Descriptions

Pin Description

V CC a 5V g 5% power supply.

V BB b 5V g 5% power supply.

GND Ground. All analog and digital signals are refer-

enced to this pin.

FS X Transmit Frame Sync input. Normally a pulse or

squarewave with an 8 kHz repetition rate is ap-

plied to this input to define the start of the transmit

time slot assigned to this device (non-delayed

data timing mode), or the start of the transmit

frame (delayed data timing mode using the inter-

nal time-slot assignment counter).

FS R Receive Frame Sync input. Normally a pulse or

squarewave with an 8 kHz repetition rate is ap-

plied to this input to define the start of the receive

time slot assigned to this device (non-delayed

data timing mode), or the start of the receive

frame (delayed data timing mode using the inter-

nal time-slot assignment counter).

BCLK Bit clock input used to shift PCM data into and out

of the D R and D X pins. BCLK may vary from 64

kHz to 4.096 MHz in 8 kHz increments, and must

be synchronous with MCLK.

MCLK Master clock input used by the switched capacitor

filters and the encoder and decoder sequencing

logic. Must be 512 kHz, 1.536 MHz, 1.544 MHz,

2.048 MHz or 4.096 MHz and synchronous with

BCLK.

VF X I The Transmit analog high-impedance input. Voice

frequency signals present on this input are encod-

ed as an A-law or m -law PCM bit stream and shift-

ed out on the selected D X pin.

VF R O The Receive analog power amplifier output, capa-

ble of driving load impedances as low as 300 X

(depending on the peak overload level required).

PCM data received on the assigned D R pin is de-

coded and appears at this output as voice fre-

quency signals.

D X 0 1 is available on the TP3070 only; D X 0is

Pin Description

D X 1 available on all devices. These Transmit Data TRI-

STATE É outputs remain in the high impedance

state except during the assigned transmit time slot

on the assigned port, during which the transmit

PCM data byte is shifted out on the rising edges of

BC LK.

TS X 0 1 is available on the TP3070 only; TS X 0is

available on all devices. Normally these open-

drain outputs are floating in a high impedance

state except when a time-slot is active o n one of

the D X outputs, when the appropriate TS X output

pulls low to enable a backplane line-driver.

D R 0 1 is available on the TP3070 only; D R 0 is avail-

able on all devices. These receive data inputs are

D R 1 inactive except during the assigned receive time

slot of the assigned port when the receive PCM

data is shifted in on the falling edges of BCLK.

CCLK Control Clock input. This clock shifts serial control

informatio n in to or out from CI/O or CI and CO

when the CS input is low, depending on the cur-

rent instruction. CCLK may be asynchronous with

the other system clocks.

CI/O This is the Control Data I/O pin which is provided

on the TP3071. Serial control information is s hift ed

to or read from COMBO II on this pin when CS is

low. The direction of the data is determined by the

current instruction as defined in Table I.

CI This is a separate Control Input, available only on

the TP3070. It can be connected to CO if required.

CO This is a separate Control Output, available only

on the TP3070. It can be connected to CI if re-

quired.

CS Chip Select input. When this pin is low, control in-

formation can be written to or read from COMBO II

via the CI/O pin (or CI and CO).

IL5±IL0 IL5 through IL0 are available on the TP3070.

IL4 through IL0 are available on the TP3071.

TS X 1

Pin Descriptions (Continued)

Pin Description

Each Interface Latch I/O pin may be individually

programmed as an input or an output determined

by the state of the corresponding bit in the Latch

Direction Register (LDR). For pins configured as

inputs, the logic state sensed on each input is

latched into the Interface Latch Register (ILR)

when eve r control data is written to COMBO II,

while CS is low, and the information is shifted out

on the CO (or CI/O) pin. When configured as out-

puts, control data written into the ILR appears at

the corresponding IL pins.

MR This logic input must be pulled low for normal op-

eration of COMBO II. When pulled momentarily

high (at least 1 m sec.), all programmable registers

in the device are reset to the states specified un-

der ``Power-On Initialization''.

NC No Connection. Do not connect to this pin. Do not

route traces through this pin.

Functional Description

POWER-ON INITIALIZATION

When power is first applied, power-on reset circuitry initializ-

es the COMBO II and puts it into the power-down state. The

gain control registers for the transmit and receive gain sec-

tions are programmed to OFF (00000000), the hybrid bal-

ance circuit is turned off, the power amp is disabled and the

device is in the non-delayed timing mode. The Latch Direc-

tion Register (LDR) is pre-set with all IL pins programmed as

inputs, placing the SLIC interface pins in a high impedance

state. The CI/O pin is set as an input ready for the first

control byte of the initialization sequence. Other initial states

in the Control Register are indicated in Section 2.0.

A reset to these same initial conditions may also be forced

by driving the MR pin momentarily high. This may be done

either when powered-up or down. For normal operation this

pin must be pulled low. If not used, MR should be hard-

wired to ground.

The desired modes for all programmable functions may be

initialized via the control port prior to a Power-up command.

POWER-DOWN STATE

Following a period of activity in the powered-up state the

power-down state may be re-entered by writing any of the

control instructions into the serial control port with the ``P''

bit set to ``1'' as indicated in Table I. It is recommended that

the chip be powered down before writing any additional in-

structions. In the power-down state, all non-essential circuit-

ry is de-activated and the D X 0 (and D X 1) outputs are in the

high impedance TRI-STATE condition.

The coefficients stored in the Hybrid Balance circuit and the

Gain Control registers, the data in the LDR and ILR, and all

control bits remain unchanged in the power-down state un-

less changed by writing new data via the serial control port,

which remains active. The outputs of the Interface Latches

also remain active, maintaining the ability to monitor and

control the SLIC.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF X I, is a high impedance sum-

ming input which is used as the differencing point for the

internal hybrid balance cancellation signal. No external

components are necessary to set the gain. Following this

circuit is a programmable gain/attenuation amplifier which is

controlled by the contents of the Transmit Gain Register

(see Programmable Functions section). An active pre-filter

then precedes the 3rd order high-pass and 5th order low-

pass switched capacitor filters. The A/D converter has a

compressing characteristic according to the standard

CCITT A or m 255 coding laws, which must be selected by a

control instruction during initialization (see Tables I and II). A

precision on-chip voltage reference ensures accurate and

highly stable transmission levels. Any offset voltage arising

in the gain-set amplifier, the filters or the comparator is can-

celed by an internal auto-zero circuit.

Each encode cycle begins immediately following the as-

signed Transmit time-slot. The total signal delay referenced

to the start of the time-slot is approximately 165 m s (due to

the Transmit Filter) plus 125 m s (due to encoding delay),

which totals 290 m s. Data is shifted out on D X 0orD X 1 dur-

ing the selected time slot on eight rising edges of BCLK.

DECODER AND RECEIVE FILTER

PCM data is shifted into the Decoder's Receive PCM Regis-

ter via the D R 0orD R 1 pin during the selected time-slot on

the 8 falling edges of BCLK. The Decoder consists of an

expanding DAC with either A or m 255 law decoding charac-

teristic, which is selected by the same control instruction

used to select the Encode law during initialization. Following

the Decoder is a 5th order low-pass switched capacitor filter

with integral Sin x/x correction for the 8 kHz sample and

hold. A programmable gain amplifier, which must be set by

writing to the Receive Gain Register, is included, and finally

a Power Amplifier capable of driving a 300 X load to g 3.5V,

a 600 X load to g 3.8V or a 15 k X load to g 4.0V at peak

overload.

A decode cycle begins immediately after the assigned re-

ceive time-slot, and 10 m s later the Decoder DAC output is

updated. The total signal delay is 10 m s plus 120 m s (filter

delay) plus 62.5 m s(

frame) which gives approximately

190 m s.

PCM INTERFACE

The FS X and FS R frame sync inputs determine the begin-

ning of the 8-bit transmit and receive time-slots respectively.

They may have any duration from a single cycle of BCLK

HIGH to one MCLK period LOW. Two different relationships

may be established between the frame sync inputs and the

actual time-slots on the PCM busses by setting bit 3 in the

Control Register (see Table II). Non-delayed data mode is

similar to long-frame timing on the TP3050/60 series of de-

vices (COMBO); time-slots begin nominally coincident with

the rising edge of the appropriate FS input. The alternative

is to use Delayed Data mode, which is similar to short-frame

sync timing on COMBO, in which each FS input must be

high at least a half-cycle of BCLK earlier than the time-slot.

The Time-Slot Assignment circuit on the device can only be

used with Delayed Data timing.

When using Time-Slot Assignment, the beginning of the first

time-slot in a frame is identified by the appropriate FS input.

The actual transmit and receive time-slots are then deter-

mined by the internal Time-Slot Assignment counters.

Transmit and Receive frames and time-slots may be

skewed from each other by any number of BCLK cycles.

During each assigned Transmit time-slot, the selected

D X 0/1 output shifts dat a o ut fro m t he PCM register on the

rising edges of BCLK. TS X 0 (or TS X 1 as appropriate) also

pulls low for the first 7 (/2 bit times of the time-slot to control

the TRI-STATE Enable of a backplane line-driver. Serial

PCM data is shifted into the selected D R 0/1 input during

each assigned Receive time-slot on the falling edges of

BCLK. D X 0orD X 1 and D R 0orD R 1 are selectable on the

TP3070 only, see Section 6.

(/2

Functional Description (Continued)

TABLE I. Programmable Register Instructions

Function

Byte 1 (Note 1) Byte 2 (Note 1)

76543210 76543210

Single Byte Power-Up/Down

P XXXXX0X None

Write Control Register

P 000001X eTable II

Read-Back Control Register

P 000011X eTable II

Write to Interface Latch Register

P 000101X eTable V

Read Interface Latch Register

P 000111X eTable V

Write Latch Direction Register

P 001001X eTable IV

Read Latch Direction Register

P 001011X eTable IV

Write Receive Gain Register

P 010001X eTable VIII

Read Receive Gain Register

P 010011X eTable VIII

Write Transmit Gain Register

P 010101X eTable VII

Read Transmit Gain Register

P 010111X eTable VII

Write Receive Time-Slot/Port

P 100101X eTable VI

Read-Back Receive Time-Slot/Port

P 100111X eTable VI

Write Transmit Time-Slot/Port

P 101001X eTable VI

Read-Back Transmit Time-Slot/Port

P 101011X eTable VI

Read Hybrid Balance Register 1 P 011011X

Write Hybrid Balance Register 2 P 011101X

Read Hybrid Balance Register 2 P 011111X

Write Hybrid Balance Register 3 P 100001X

Read Hybrid Balance Register 3 P 100011X

Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CI/O pin. X e don't care.

Note 2: ``P'' is the power-up/down control bit, see ``Power-Up/Down Control'' section. (``0'' e Power Up, ``1'' e Power Down)

Note 3: Other register address codes are invalid and should not be used.

P 011001X

Derive from

Optimization

Routine in

TP3077SW

Program

SERIAL CONTROL PORT

Control information and data are written into or read-back

from COMBO II via the serial control port consisting of the

control clock CCLK, the serial data input/output CI/O, (or

separate input, CI, and out put , CO, on the TP3070 only),

and the Chip Select input, CS. All control instructions re-

quire 2 bytes, as listed in Table I, with the exception of a

single byte power-up/down command. The byte 1 bits are

used as follows: bit 7 specifies power up or power down;

bits 6, 5, 4 and 3 specify the register address; bit 2 specifies

whether the instruction is read or write; bit 1 specifies a one

or two byte instruction; and bit 0 is not used.

To shift contr ol d ata into COMBO II, CCLK must be pulsed 8

times while CS is low. Data on the CI/O (or CI) input is

shifted into the serial input register on the falling edge of

each CCLK pulse. After all data is shifted in, the contents of

the input shift register are decoded, and may indicate that a

2nd byte of control data will follow. This sec ond byte may

either be defined by a second byte-wide CS pulse or m ay

follow the first contiguously, i.e. it is not mandatory for CS to

return high between the first and second control bytes. At

the end of CCLK8 in the 2nd control byte th e da ta is loaded

into the appropriate programmable register. CS may remain

low continuously wh en programming successive registers, if

desired. However, CS should be set high when no data

transfers are in progress.

To readback Interface Latch data or status information from

COMBO II, the firs t byte of the appropriate in str uction is

strobed in while CS is low, as defined in Table I. CS must be

kept low, or be taken low again for a further 8 CCLK cycles,

during which the data is shifted o nto the CO or CI/O pin on

the rising edges of CCLK. When CS is high the CO or CI/O

pin is in the high-impedance TRI-STATE, enabling the CI/O

pi ns of many devices to be multiplexed together.

If CS returns high during either byte 1 or byte 2 before all

eight CCLK pulses of that byte occur, both the bit count and

byte count are reset and register contents are not affected.

This prevents loss of synchronization in the control interface

as well as corruption of regist er d ata due to processor inter-

rupt or other problem. When CS returns low again, the de-

vice will be ready to accept bit 1 of byte 1 of a new instruc-

tion.

Programmable Functions

1.0 POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and power-down

control may be accomplished by writing any of the control

instructions listed in Table I into COMBO II with the ``P'' bit

set to ``0'' for power-up or ``1'' for power-down. Normally it is

recommended that all programmable functions be initially

programmed while the device is powered down. Power state

control can then be included with the last programming in-

struction or the separate single-byte instruction. Any of the

programmable registers may also be modified while the de-

vice is powered-up or down by setting the ``P'' bit as indicat-

ed. When the power-up or down control is entered as a

single byte instruction, bit one (1) must be reset to a 0.

When a power-up command is given, all de-activated cir-

cuits are activated, but the TRI-STATE PCM output(s), D X 0

(and D X 1), will remain in the high impedance state until the

second FS X pulse after power-up.

Write Hybrid Balance Register 1

Programmable Functions (Continued)

2.0 CONTROL REGISTER INSTRUCTION

The first byte of a READ or WRITE instruction to the Control

following bit functions:

2.4 Digital Loopback

Digital Loopback mode is entered by setting the ``AL'' and

``DL'' bits in the Control Register as shown in Table II. This

mode provides another stage of path verification by en-

abling data written into the Receive PCM Register to be

read back from that register in any Transmit time-slot at

D X 0/1. In digital loopback, the decoder will remain function-

al and output a signal at VF R O. If this is undesirable, the

receive output can be turned off by programming the re-

ceive gain register to all zeros.

3.0 INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface Latches as-

sume they are inputs, and therefore all IL pins are in a high

impedance state. Each IL pin may be individually pro-

grammed as a logic input or output by writing the appropri-

ate instruction to the LDR, see Tables I and IV. For minimum

power dissipation, unconnected latch pins should be pro-

grammed as outputs. For the TP3071, L5 should always be

programmed as an output.

Bits L 5 ±L 0 must be set by writing the specified instruction to

the LDR with the L bits in the second byte set as follows:

TABLE IV. Byte 2 Functions of Latch Direction Register

Byte 2 Bit Number

7 6 5 4 3 2 1 0

L 0 L 1 L 2 L 3 L 4 L 5 XX

TABLE II. Control Register Byte 2 Functions

Bit Number and Name

7 6 5 4 3 2 1 0

Function

F 1 F 0 MA IA DN DL AL PP

0 0 MCLK e 512 kHz

0 1 MCLK e 1.536 or 1.544 MHz

1 0 MCLK e 2.048 MHz*

1 1 MCLK e 4.096 MHz

0 X Select m -255 law*

1 0 A-law, Including Even Bit

Inversion

1 1 A-law, No Even Bit Inversion

0 Delayed Data Timing

1 Non-Delayed Data Timing*

0 0 Normal Operation*

1 X Digital Loopback

0 1 Analog Loopback

0 Power Amp Enabled in PDN

1 Power Amp Disabled in PDN*

* e State at power-on initialization. (Bit 4 e 0)

2.1 Master Clock Frequency Selection

A Master clock must be provided to COMBO II for operation

of the filter and coding/decoding functions. The MCLK fre-

quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,

2.048 MHz, or 4.096 MHz and must be synchronous with

BCLK. Bits F 1 and F 0 (see Table II) must be set during

initialization to select the correct internal divider.

2.2 Coding Law Selection

Bits ``MA'' and ``IA'' in Table II permit the selection of m 255

coding or A-law coding, with or without even bit inversion.

2.3 Analog Loopback

Analog Loopback mode is entered by setting the ``AL'' and

``DL'' bits in the Control Register as shown in Table II. In the

analog loopback mode, the Transmit input VF X I is isolated

from the input pin and internally connected to the VF R O

output, forming a loop from the Receive PCM Register back

to the Transmit PCM Register. The VF R O pin remains ac-

tive, and the programmed settings of the Transmit and Re-

ceive gains remain unchanged, thus care must be taken to

ensure that overload levels are not exceeded anywhere in

the loop. Hybrid balance must be disabled for meaningful

analog loopback function.

Bit

IL Direction

Input

Output

X e don't care

4.0 INTERFACE LATCH STATES

Interface Latches configured as outputs assume the state

determined by the appropriate data bit in the 2-byte instruc-

tion written to the Interface Latch Register (ILR) as shown in

Tables I and V. Latches configured as inputs will sense the

state applied by an external source, such as the Off-Hook

detect output of a SLIC. All bits of the ILR, i.e. sensed inputs

and the programmed state of outputs, can be read back in

the 2nd byte of a READ from the ILR.

It is recommended that during initialization, the state of IL

pins to be configured as outputs should be programmed

first, followed immediately by the Latch Direction Register.

TABLE V. Interface Latch Data Bit Order

Bit Number

7 6 5 4 3 2 1 0

D 0 D 1 D 2 D 3 D 4 D 5 XX

TABLE III. Coding Law Conventions

m 255 law

True A-law with

A-law without

even bit inversion

MSB LSB

V IN ea Full Scale

10000000

10101010

11111111

V IN e 0V

11111111

11010101

10000000

01111111

01010101

00000000

V IN eb Full Scale

00000000

00101010

01111111

Note 1: The MSB is always the first PCM bit shifted in or out of COMBO II.

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