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Texas Instruments Incorporated
Data Acquisition
Clock jitter analyzed in the time
domain, Part 2
By Thomas Neu
Systems and Applications Engineer
Introduction
Part 1 of this three-part article series
focused on how to accurately estimate
jitter from a clock source and combine it
with the aperture jitter of an ADC. In this
article, Part 2, that combined jitter will be
used to calculate the ADC’s signal-to-noise
ratio (SNR), which will then be compared
against actual measurements.
Measurements with filtered
sampling clock
An experiment was set up to see how well
the measured clock phase noise matched
the clock jitter extracted from the ADC’s
measured SNR. As shown in Figure 11, a
Texas Instruments (TI) CDCE72010 with a
Toyocom 491.52-MHz VCXO was used to
generate a 122.88-MHz sampling clock, and
the filtered phase-noise output was mea-
sured with the E5052A from Agilent. Two
different TI data converters (ADS54RF63
and ADS5483) were evaluated by using an
input frequency whose SNR was predomi-
nantly limited by the sampling-clock jitter.
The size of the fast Fourier transform
(FFT) was chosen to be 131,000 points.
The plot in Figure 12 illustrates the mea-
sured output phase noise of the filtered
CDCE72010 LVCMOS output. An FFT size
of 131,000 points sets the lower integration
bandwidth to ~500 Hz. The upper integra-
tion limit is set by the bandpass filter, whose
effect is clearly visible in the phase-noise
plot. Phase noise beyond the bandpass-filter
limit shown in the plot is the noise floor of
the E5052A and should not be included in
the jitter calculation. The integration of the
filtered phase-noise output resulted in a
clock jitter of ~90 fs.
Next, a baseline for the thermal noise was
established. Both ADCs were sampled with
a filtered sampling clock directly from the
clock-source generator with ~35 fs of jitter,
and the CDCE72010 was bypassed. The input frequency
was set to 10 MHz, where no impact on the SNR from clock
jitter was expected. Then the aperture jitter for each ADC
was determined by increasing the input frequency to where
Figure 11. Test setup for correlation with filtered clock
491.52 MHz
CDCE72010
Clock Synchronizer
and
Jitter Cleaner
Clock-Source
Generator
VCXO
10-MHz
Reference
122.88-MHz
Clock
E5052A
Signal-Source
Analyzer
Signal-Source
Generator
Bandpass
Filter
Bandpass
Filter
f
IN
ADS54RF63
ADS5483
Figure 12. Measured phase noise of the filtered clock
0
Limit Due to
Bandpass Filter
–20
–40
500 Hz to 7 MHz
t
= 90 fs
–60
Jitter
–80
–100
–120
Noise Floor
of E5052A
–140
–160
–180
100
1 k
10 k
100 k
1 M
10 M
100 M
Frequency Offset (Hz)
the SNR was mainly jitter-limited. Since the sampling-clock
jitter is much lower than the estimated ADC aperture jitter,
the calculation should be very accurate. It is also impor-
tant to remember that the output amplitude of the clock
5
Analog Applications Journal
4Q 2010
www.ti.com/aaj
High-Performance Analog Products
Data Acquisition
Texas Instruments Incorporated
source should be increased (but not so much
that it exceeds the maximum ratings of the
ADC), boosting the slew rate of the clock signal
until the SNR levels off.
Since it is known that the external clock jitter
from the filtered output of the clock-source gen-
erator is ~35 fs, the ADC aperture jitter can be
calculated by using the measured SNR results
and solving Equations 1, 2, and 3 in Part 1
(Reference 1) for aperture jitter. Please see
Equation 4 below. The measured SNR results as
well as the calculated aperture jitter for each
ADC are listed in Table 3.
With the ADC aperture jitter and the sampling-
clock jitter of the CDCE72010, the ADC’s SNR
can be calculated and compared against the
actual measurement. Using the ADC aperture
jitter permits the sampling-clock jitter of the
CDCE72010 to be calculated from the measured
SNR values, as illustrated in Table 4. At first
glance the predicted SNR values are somewhat
close to the measured values. However, compar-
ing the calculated sampling-clock jitter for the
two ADCs against the measured value of 90 fs
reveals a different picture. There is quite a bit of mismatch.
The reason for the mismatch is that the calculated aper-
ture jitter is based on the fast slew rate of the clock-source
generator. The bandpass filter on the LVCMOS output of
the CDCE72010 eliminates the higher-order harmonics of
Figure 13. Impact of clock filter on sampling
clock’s slew rate
LVCMOS
(No Bandpass Filter)
LVCMOS
with
Bandpass Filter
Clock Generator
with Bandpass Filter
Time (1 ns/div)
the clock signal that help create fast rising and falling
edges. The scope plot in Figure 13 demonstrates how the
bandpass filter drastically reduces the slew rate of the
unfiltered LVCMOS output and turns the square wave into
a sine wave.
2
2
2
SNR
SNR
Measured
Thermal Noise
−
−
−
20
20
10
10
2
t
=
−
(t
)
(4)
Aperture _ ADC
Jitter,Clock _ Input
2f
π×
IN
Table 3. Measured SNR and calculated jitter
THERMAL NOISE
(MEASURED SNR AT f
IN
= 10 MHz)
(dBFS)
MEASURED SNR AT HIGH f
IN
(JITTER-LIMITED)
(dBFS)
CALCULATED
APERTURE JITTER
(fs)
DEVICE
ADS54RF63
64.4
61.0 (f
IN
= 1 GHz)
~115
ADS5483
79.1
78.2 (f
IN
= 100 MHz)
~85
Table 4. SNR results with 90-fs clock jitter
CALCULATED SNR WITH
90-fs CLOCK JITTER
(dBFS)
CALCULATED JITTER FROM
MEASURED SNR
(fs)
MEASURED SNR
(dBFS)
DEVICE
ADS54RF63 (f
IN
= 1 GHz)
59.9
58.7
~130
ADS5483 (f
IN
= 100 MHz)
77.8
77.1
~125
6
High-Performance Analog Products
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4Q 2010
Analog Applications Journal
Texas Instruments Incorporated
Data Acquisition
One way to improve the slew rate is to add a low-noise
RF amplifier with a fair amount of gain between the
LVCMOS output of the CDCE72010 and the bandpass filter
(see Figure 14). The amplifier should be placed before the
filter so that its noise contribution to the clock signal is
limited to the filter bandwidth and not to the clock input
bandwidth of the ADC. Since the amplifier in the next
experiment has a gain of 21 dB, a variable attenuator was
added after the bandpass filter to match the slew rate of
the filtered LVCMOS signal to the filtered output of the
clock generator. The attenuator also protects the clock
input of the ADCs from exceeding the maximum ratings.
With the low-noise RF amplifier included in the clock’s
input path, the SNR measurement at high input frequency
was repeated for both data converters. The results are
shown in Table 5. It can be observed that the measured
SNR matches the predicted SNR very well. Using Equa-
tion 5 below provided calculated clock-jitter values that
are within 5 fs of the 90-fs clock jitter, which was derived
from the phase-noise measurement.
Figure 14. RF amplifier added in front of
bandpass filter to reduce slew rate
CDCE72010
RFAmplifier
0.002 to 500 MHz
Gain = 21 dB
Experiment with unfiltered sampling clock
To stress the importance of filtering the sampling clock, the
clock bandpass filter was removed from the CDCE72010
output in the next experiment. The E5052A phase-noise
analyzer was used to capture the clock phase noise as
shown in the setup in Figure 15. Unfortunately, however,
Table 5. SNR results with 90-fs clock jitter and RF amplifier
CALCULATED SNR WITH
90-fs CLOCK JITTER
(dBFS)
MEASURED SNR
WITH RF AMPLIFIER
(dBFS)
CALCULATED JITTER FROM
MEASURED SNR
(fs)
DEVICE
ADS54RF63 (f
IN
= 1 GHz)
59.9
60.0
~85
ADS5483 (f
IN
= 100 MHz)
77.8
77.6
~95
2
2
2
SNR
SNR
Measured
Thermal Noise
−
−
−
20
20
10
10
2
t
=
−
(t
)
(5)
Jitter,Clock _ Input
Aperture _ ADC
2f
π×
IN
Figure 15. Test setup for unfiltered sampling-clock input
491.52 MHz
CDCE72010
Clock Synchronizer
and
Jitter Cleaner
Clock-Source
Generator
VCXO
10-MHz
Reference
E5052A
Signal-Source
Analyzer
Signal-Source
Generator
122.88-MHz
Clock
Bandpass
Filter
f
IN
ADS54RF63
ADS5483
7
Analog Applications Journal
4Q 2010
www.ti.com/aaj
High-Performance Analog Products
Data Acquisition
Texas Instruments Incorporated
the analyzer measures the phase noise only up to a 40-MHz
offset of the carrier frequency and doesn’t give any clue
about the phase-noise characteristic beyond that point.
To set the correct upper integration limit when an
unfiltered clock is used, the sampling theory has to be
reviewed again. The unfiltered clock output of the
CDCE72010 looks like a square wave with fast rising and
falling edges caused by the higher-order harmonics of the
fundamental sinusoid of the clock frequency. These har-
monics have lower amplitude than the fundamental, and
their amplitude decreases as the harmonic order increases.
At the sampling instant, both the fundamental sine wave
and the higher-order harmonics mix with the input signal
as illustrated in Figure 16. (For simplification, only one
harmonic is shown.) Therefore, the phase noise around
the third-order harmonic (for example) mixes with the
input signal, and the third harmonic creates a mixing
product as well. However, since the third harmonic of the
clock signal has lower amplitude, the amplitude of this
mixing product is also reduced.
When the two sampled signals are combined, it can be
seen that the overall degradation of the phase noise
caused by the third harmonic becomes minimal once the
amplitude difference exceeds ~3 dB. Since the crossover
point between the fundamental and the third harmonic is
at 2 × f
s
, integrating the wideband phase noise to 2 × f
s
should give a fairly accurate result.
As shown later in Figure 19, the phase noise of the
unfiltered LVCMOS output of the CDCE72010 levels out
around –153 dBc/Hz, starting at an offset frequency of
Figure 16. Clock fundamental and its harmonics mix with input signal
at sampling instant
Clock Signal
Third Harmonic
of
Clock Signal
x dB
Clock Phase
Noise
f
s
2 x f
s
3 x f
s
Input Signal
ADC
Input Signal
Sampled with f
S
Input Signal
Sampled with 3 x f
S
x dB
f
IN
x dB
f
IN
f
IN
Both samples get
combined at sampling
instant
Phase-noise
contribution from 3 x f
can be neglected
S
x dB
f
IN
8
High-Performance Analog Products
www.ti.com/aaj
4Q 2010
Analog Applications Journal
Texas Instruments Incorporated
Data Acquisition
Table 6. SNR results with 1.27-ps clock jitter
CALCULATED SNR WITH
1.27-ps CLOCK JITTER
(dBFS)
CALCULATED JITTER FROM
MEASURED SNR
(fs)
MEASURED SNR
(dBFS)
DEVICE
ADS54RF63 (f
IN
= 1 GHz)
42.8
51.35
~450
~10 MHz, which is likely due to the thermal noise of the
LVCMOS output buffer. The ADS54RF63 EVM has a clock
input bandwidth of ~1 GHz (limited by the transformer);
hence, theoretically the phase noise should be integrated
to ~1 GHz (rolling off at 3 dB at a 900-MHz offset). This
would result in ~1.27 ps of sampling-clock jitter and would
reduce the SNR at f
IN
= 1 GHz to ~42.8 dBFS!
The actual SNR measurement was quite a bit better
than that, as demonstrated in Table 6. There is a huge gap
between the calculated clock jitter and the SNR compared
to the actual measurement. This suggests that the phase
noise of the LVCMOS output indeed is limited well before
the 900-MHz offset boundary set by the transformer.
To prove that the phase noise of the unfiltered clock
signal needs to be integrated to roughly twice the sampling
frequency, the following experiment was set up: Different
low-pass filters were added between the CDCE72010 out-
put and the clock input of the ADS54RF63.
It is important to remember that a low-pass filter with a
bandwidth of less than 3x the clock frequency reduces the
slew rate of the clock signal just like the bandpass filter
did in the earlier experiment. The low-pass filter elimi-
nates the higher-order harmonics that produce the faster
rise time and slew rate of the clock signal, thus increasing
the aperture jitter of the ADC. For that reason, the same
low-noise RF amplifier from the earlier experiment was
added to the clock path, and the slew rate was matched to
the signal generator by using the variable attenuator (see
Figure 17).
Figure 17. RF amplifier added in front of
low-pass filter to reduce slew rate
CDCE72010
RFAmplifier
0.002 to 500 MHz
Gain = 21 dB
Using low-pass filters with different corner frequencies
on the sampling clock of the ADS54RF63 (as depicted in
Figure 18) resulted in the interesting values in Table 7.
The results of this experiment suggest that the phase-
noise impact of the LVCMOS output on the clock jitter is
limited to roughly 200 to 250 MHz, which corresponds to
an 80- to 130-MHz offset from the 122.88-MHz clock signal
and is approximately 2x the sampling frequency. Therefore,
Table 7. Measured SNR for ADS54RF63
MEASURED SNR AT f
IN
= 1 GHz
(dBFS)
FILTER TYPE
Unfiltered Clock
51.35
140-MHz Low-Pass Filter
54.01
200-MHz Low-Pass Filter
51.81
Figure 18. Different low-pass filters limit phase noise
Low-Pass
Filter
Clock Signal
Third Harmonic
of
Clock Signal
f
s
2 x f
s
3 x f
s
9
Analog Applications Journal
4Q 2010
www.ti.com/aaj
High-Performance Analog Products
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