2N3904.PDF

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DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
M3D186
2N3904
NPN switching transistor
Product specification
Supersedes data of September 1994
File under Discrete Semiconductors, SC04
1997 Jul 15
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Philips Semiconductors
Product specification
NPN switching transistor
2N3904
FEATURES
PINNING
·
Low current (max. 200 mA)
PIN
DESCRIPTION
·
Low voltage (max. 40 V).
1
collector
2
base
APPLICATIONS
3
emitter
·
High-speed switching.
DESCRIPTION
handbook, halfpag 1
1
2
NPN switching transistor in a TO-92; SOT54 plastic
package. PNP complement: 2N3906.
3
2
MAM279
3
Fig.1 Simplified outline (TO-92; SOT54)
and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V CBO
collector-base voltage
open emitter
-
60
V
V CEO
collector-emitter voltage
open base
-
40
V
I C
collector current (DC)
-
200
mA
P tot
total power dissipation
T amb £
25
°
C
-
500
mW
h FE
DC current gain
I C = 10 mA; V CE = 1 V
100
300
f T
transition frequency
I C = 10 mA; V CE = 20 V; f = 100 MHz
300
-
MHz
t off
turn-off time
I Con = 10 mA; I Bon = 1 mA; I Boff =
-
1mA
-
240
ns
1997 Jul 15
2
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Philips Semiconductors
Product specification
NPN switching transistor
2N3904
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V CBO
collector-base voltage
open emitter
-
60
V
V CEO
collector-emitter voltage
open base
-
40
V
V EBO
emitter-base voltage
open collector
-
6
V
I C
collector current (DC)
-
200
mA
I CM
peak collector current
-
300
mA
I BM
peak base current
-
100
mA
P tot
total power dissipation
T amb £ 25 ° C; note 1
-
500
mW
T stg
storage temperature
-
65
+150
°
C
T j
junction temperature
-
150
°
C
T amb
operating ambient temperature
-
65
+150
°
C
Note
1. Transistor mounted on an FR4 printed-circuit board.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R th j-a
thermal resistance from junction to ambient note 1
250
K/W
Note
1. Transistor mounted on an FR4 printed-circuit board.
CHARACTERISTICS
T amb =25
°
C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
I CBO
collector cut-off current
I E = 0; V CB =30V
-
50
nA
I EBO
emitter cut-off current
I C = 0; V EB =6V
-
50
nA
h FE
DC current gain
V CE = 1 V; note 1
I C = 0.1 mA
60
-
I C = 1 mA
80
-
I C = 10 mA
100
300
I C =50mA
60
-
I C = 100 mA
30
-
V CEsat
collector-emitter saturation voltage I C = 10 mA; I B = 1 mA; note 1
-
200
mV
I C = 50 mA; I B = 5 mA; note 1
-
200
mV
V BEsat
base-emitter saturation voltage
I C = 10 mA; I B = 1 mA; note 1
-
850
mV
I C = 50 mA; I B = 5 mA; note 1
-
950
mV
C c
collector capacitance
I E =i e = 0; V CB =5V; f=1MHz
-
4
pF
C e
emitter capacitance
I C =i c = 0; V EB = 500 mV; f = 1 MHz
-
8
pF
f T
transition frequency
I C = 10 mA; V CE = 20 V; f = 100 MHz
300
-
MHz
1997 Jul 15
3
337921123.029.png
Philips Semiconductors
Product specification
NPN switching transistor
2N3904
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
F
noise figure
I C = 100
m
A; V CE =5V; R S =1k
W
;
-
5
dB
f = 10 Hz to 15.7 kHz
Switching times (between 10% and 90% levels); see Fig.2
t on
turn-on time
I Con = 10 mA; I Bon = 1 mA; I Boff = - 1mA
-
65
ns
t d
delay time
-
35
ns
t r
rise time
-
35
ns
t off
turn-off time
-
240
ns
t s
storage time
-
200
ns
t f
fall time
-
50
ns
Note
1. Pulse test: t p £
300
m
s;
0.02.
andbook, full pagewidth
V BB
V CC
R B
R C
oscilloscope
(probe)
450
V o
(probe)
450
oscillo scope
W
W
V i
R2
DUT
R1
MLB826
3 ns.
R1 = 56 W ; R2 = 2.5 k W ; R B = 3.9 k W ; R C = 270 W .
V BB =
m
s; t p =10
m
s; t r =t f £
1.9 V; V CC =3V.
Oscilloscope input impedance Z i =50
-
W
.
Fig.2 Test circuit for switching times.
1997 Jul 15
4
d£
V i = 5 V; T = 500
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Philips Semiconductors
Product specification
NPN switching transistor
2N3904
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
2
e 1
D
e
3
b 1
L 1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b 1
0.66
0.56
c
D
d
E
e
e 1
L
L 1 (1)
mm
5.2
5.0
0.48
0.40
0.45
0.40
4.8
4.4
1.7
1.4
4.2
3.6
2.54
1.27
14.5
12.7
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
REFERENCES
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT54
TO-92
SC-43
97-02-28
1997 Jul 15
5
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