4536.pdf

HCC/HCF4536B

. 24 FLIP-FLOP STAGES - COUNTS FROM

PROGRAMMABLE TIMER

. LAST 16 STAGES SELECTABLE BY BCD SE-

. BYPASS INPUT ALLOWS BYPASSING FIRST

8 STAGES

LECT CODE

. ON-CHIP RC OSCILLATOR PROVISION

. SCHMITT-TRIGGER IN CLOCK LINE PER-

MITS OPERATION WITH VERY LONG RISE

AND FALL TIMES

(Plastic Package)

(Ceramic Package)

. ON-CHIP MONOSTABLE OUTPUT PROVI-

. TEST MODE ALLOWS FAST TEST SE-

(Chip Carrier)

. SET AND RESET INPUTS

. CAPABLE OF DRIVING TWO LOW POWER

TTL LOADS, ONE LOWER-POWER

SCHOTTKY LOAD, OR TWO HTL LOADS

OVER THE RATED TEMPERATURE RANGE

ORDER CODES :

HCC4536BF

HCF4536BEY

HCF4536BC1

. STANDARDIZED, SYMMETRICAL OUTPUT

CHARACTERISTICS

. QUIESCENT CURRENT AT 20V FOR HCC DE-

PIN CONNECTIONS

. 5V, 10V, AND 15V PARAMETRIC RATINGS

. INPUT CURRENT OF 100 nA AT 18V AND 25 ° C

. 100% TESTED FOR QUIESCENT CURRENT

. MEETS ALL REQUIREMENTS OF JEDEC TEN-

TATIVE STANDARD N o . 13A, ”STANDARD

SPECIFICATIONS FOR DESCRIPTION OF ”B”

SERIES CMOS DEVICES”

DESCRIPTION

The HCC4536B (extended temperature range) and

HCF4536B (intermediate temperature range) are

monolithic integrated circuits, available in 16-lead

dual in-line plastic or ceramic package. The

HCC/HCF4536B is a programmable timer consi-

sting of 24 ripple-binary counter stages. The salient

feature of this device is its flexibility. The device can

count from 1 to 2 24 or the first 8 stages can be by-

passed to allow an output, selectable by a 4-bit co-

de, from any one of the remaining 16 stages. It can

be driven by an external clock or an RC oscillator

that can be constructed using on-chip components.

November 1996

1/17

2 0 TO 2 24

. CLOCK INHIBIT INPUT

. TYPICAL f CL = 3MHz AT V DD = 10V

SION

QUENCE

VICE

FOR HCC DEVICE

HCC/HCF4536B

Input IN1 serves as either the external clock input or

the input to the on-chip RC oscillator. OUT1 and

OUT2 are connection terminals for the external RC

components. In addition, an on-chip monostable cir-

cuit is provided to allow a variable pulse width out-

put. Various timing functions can be achieved using

combinations of these capabilities. A logic 1 on the

8-BYPASS input enables a bypass of the first 8 sta-

ges and makes stage 9 the first counter stage of the

last 16 stages. Selection of 1 of 16 outputs is accom-

plished by the decoder and the BCD inputs A, B, C

or higher, disa-

bles the one-shot circuit and connects the decoder

directly to the DECODE OUT terminal. A resistor to

V DD and a capacitor to ground from the MONO IN

terminal enables the one-shot circuit and controls its

pulse width. A fast test mode is enabled by a logic

1 on 8-BYPASS, SET, and RESET. This mode di-

vides the 24-stage counter into three 8-stage sec-

tions to facilitate a fast test sequence.

FUNCTIONAL DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V DD *

Supply Voltage : HCC Types

HCF Types

– 0.5 to + 20

– 0.5 to + 18

V i

Input Voltage

– 0.5 to V DD + 0.5

I I

DC Input Current (any one input)

P tot

Total Power Dissipation (per package)

Dissipation per Output Transistor

for T op = Full Package-temperature Range

200

100

T op

Operating Temperature : HCC Types

HCF Types

– 55 to + 125

–40to+85

Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.

* All voltages are with respect to V SS (GND).

Storage Temperature

– 65 to + 150

2/17

and D. MONO IN is the timing input for the on-chip

monostable oscillator. Grounding of the MONO IN

terminal through a resistor of 10K

T stg

HCC/HCF4536B

BLOCK DIAGRAM

TRUTH TABLE

DECODE OUT SELECTION TABLE

In1 Set Reset

Clock

Inh

Osc

Inh

Out1 Out2

Decode

Out

DC BA

8-BYPASS = 0 8-BYPASS = 1

Number or Stages

I n Divider Chain

–

– \ –

Change

Advance

to Next

State

X1 0 0 0 0 1 1

X0 1 0 0 0 1 0

– \ –

–

X0 0 1 0

Change

00 0 0 X 0 1

Change

/ –

\ –

/ –

Advance

to Next

State

10 0 0

0 = Low Level

3/17

– \ –

HCC/HCF4536B

LOGIC DIAGRAMS (continued on next page)

4/17

HCC/HCF4536B

LOGIC DIAGRAMS (continued)

5/17

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