GAL20V8.PDF

(561 KB) Pobierz

Specifications GAL20V8

GAL20V8

High Performance E 2 CMOS PLD

Generic Array Logic™

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• HIGH PERFORMANCE E 2 CMOS ® TECHNOLOGY

— 5 ns Maximum Propagation Delay

— Fmax = 166 MHz

— 4 ns Maximum from Clock Input to Data Output

— UltraMOS ® Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

• ACTIVE PULL-UPS ON ALL PINS

•E 2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 24-pin PAL ® Devices with Full Func-

tion/Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/CLK

I

IMUX

I

CLK

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

I/O/Q

8

OLMC

I

OE

I

I

I/OE

IMUX

DESCRIPTION

The GAL20V8C, at 5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E 2 ) floating gate technology to provide the highest speed

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configu-

rations possible with the GAL20V8 are the PAL architectures

listed in the table of the macrocell description section. GAL20V8

devices are capable of emulating any of these PAL architectures

with full function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete

AC, DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write

cycles and data retention in excess of 20 years are specified.

PIN CONFIGURATION

DIP

PLCC

1

24

Vcc

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/CLK

I

I

I

I

I

GAL

20V8

4

2

28

26

I

I

I

5

25

I/O/Q

I/O/Q

7

6

23

I/O/Q

GAL20V8

Top View

NC

NC

18

I

I

I

I

I

9

21

I/O/Q

I/O/Q

I

I

I

11

19

I/O/Q

12

14

16

18

I/O/Q

I

I/OE

GND

12

13

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

July 1997

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

1

20v8_02

1146162464.373.png

1146162464.390.png

1146162464.405.png

1146162464.006.png

1146162464.017.png

1146162464.030.png

1146162464.051.png

1146162464.072.png

1146162464.093.png

1146162464.114.png

1146162464.135.png

1146162464.155.png

1146162464.166.png

1146162464.177.png

1146162464.188.png

1146162464.203.png

1146162464.214.png

1146162464.225.png

1146162464.238.png

1146162464.251.png

1146162464.262.png

1146162464.273.png

1146162464.290.png

1146162464.301.png

1146162464.312.png

1146162464.323.png

1146162464.341.png

1146162464.362.png

1146162464.384.png

1146162464.386.png

1146162464.387.png

1146162464.388.png

1146162464.389.png

1146162464.391.png

1146162464.392.png

1146162464.393.png

1146162464.394.png

1146162464.395.png

1146162464.396.png

1146162464.397.png

1146162464.398.png

1146162464.399.png

1146162464.400.png

1146162464.401.png

1146162464.402.png

1146162464.403.png

1146162464.404.png

1146162464.406.png

1146162464.407.png

1146162464.408.png

1146162464.409.png

1146162464.410.png

1146162464.001.png

1146162464.002.png

1146162464.003.png

1146162464.004.png

1146162464.005.png

1146162464.007.png

1146162464.008.png

1146162464.009.png

1146162464.010.png

1146162464.011.png

1146162464.012.png

1146162464.013.png

1146162464.014.png

1146162464.015.png

1146162464.016.png

1146162464.018.png

1146162464.019.png

1146162464.020.png

1146162464.021.png

1146162464.022.png

1146162464.023.png

1146162464.024.png

1146162464.025.png

1146162464.026.png

1146162464.027.png

1146162464.028.png

1146162464.029.png

1146162464.031.png

1146162464.032.png

1146162464.033.png

1146162464.034.png

1146162464.035.png

1146162464.036.png

1146162464.037.png

1146162464.038.png

1146162464.039.png

1146162464.040.png

1146162464.041.png

1146162464.042.png

1146162464.043.png

1146162464.044.png

1146162464.045.png

1146162464.046.png

1146162464.047.png

1146162464.048.png

1146162464.049.png

1146162464.050.png

1146162464.052.png

1146162464.053.png

1146162464.054.png

1146162464.055.png

1146162464.056.png

1146162464.057.png

1146162464.058.png

1146162464.059.png

1146162464.060.png

1146162464.061.png

1146162464.062.png

1146162464.063.png

1146162464.064.png

1146162464.065.png

1146162464.066.png

1146162464.067.png

1146162464.068.png

1146162464.069.png

1146162464.070.png

1146162464.071.png

1146162464.073.png

1146162464.074.png

1146162464.075.png

1146162464.076.png

1146162464.077.png

1146162464.078.png

1146162464.079.png

1146162464.080.png

1146162464.081.png

1146162464.082.png

1146162464.083.png

1146162464.084.png

1146162464.085.png

1146162464.086.png

1146162464.087.png

1146162464.088.png

1146162464.089.png

1146162464.090.png

1146162464.091.png

1146162464.092.png

1146162464.094.png

1146162464.095.png

1146162464.096.png

1146162464.097.png

1146162464.098.png

1146162464.099.png

1146162464.100.png

1146162464.101.png

1146162464.102.png

1146162464.103.png

1146162464.104.png

1146162464.105.png

1146162464.106.png

1146162464.107.png

1146162464.108.png

1146162464.109.png

1146162464.110.png

1146162464.111.png

1146162464.112.png

1146162464.113.png

1146162464.115.png

1146162464.116.png

1146162464.117.png

1146162464.118.png

1146162464.119.png

1146162464.120.png

1146162464.121.png

1146162464.122.png

1146162464.123.png

1146162464.124.png

1146162464.125.png

1146162464.126.png

1146162464.127.png

1146162464.128.png

1146162464.129.png

1146162464.130.png

1146162464.131.png

1146162464.132.png

1146162464.133.png

1146162464.134.png

1146162464.136.png

1146162464.137.png

1146162464.138.png

1146162464.139.png

1146162464.140.png

1146162464.141.png

1146162464.142.png

1146162464.143.png

1146162464.144.png

1146162464.145.png

1146162464.146.png

1146162464.147.png

1146162464.148.png

1146162464.149.png

1146162464.150.png

1146162464.151.png

1146162464.152.png

Specifications GAL20V8

GAL20V8 ORDERING INFORMATION

Commercial Grade Specifications

T

(

T

(

T

(

I

(

O

#

P

5

3

4

1

G

2

P

7

7

5

1

2

P

G

C

-

1

G

2

P

D

1

G

2

P

1

1

7

1

2

P

G

C

-

1

G

2

P

D

1

G

2

P

1

1

1

5

G

2

P

D

5

G

2

P

9

G

2

P

D

9

G

2

P

2

1

1

5

G

2

P

D

5

G

2

P

9

G

2

P

D

9

G

2

P

Industrial Grade Specifications

T

(

T

(

T

(

I

(

O

#

P

1

1

7

1

2

P

G

C

-

1

G

2

P

D

1

G

2

P

1

1

1

1

G

2

P

D

1

G

2

P

2

1

1

6

G

2

P

D

6

G

2

P

2

1

1

6

G

2

P

D

6

G

2

P

1

G

2

P

D

1

G

2

P

PART NUMBER DESCRIPTION

_

XXXXXXXX

XX

X

X

X

GAL20V8C

GAL20V8B

Device Name

Grade

Blank = Commercial

I = Industrial

Speed (ns)

L = Low Power

Q = Quarter Power

Power

Package

P = Plastic DIP

J = PLCC

2

1146162464.153.png

1146162464.154.png

1146162464.156.png

1146162464.157.png

1146162464.158.png

1146162464.159.png

1146162464.160.png

1146162464.161.png

1146162464.162.png

1146162464.163.png

1146162464.164.png

1146162464.165.png

1146162464.167.png

1146162464.168.png

1146162464.169.png

1146162464.170.png

1146162464.171.png

1146162464.172.png

1146162464.173.png

1146162464.174.png

1146162464.175.png

1146162464.176.png

1146162464.178.png

1146162464.179.png

1146162464.180.png

1146162464.181.png

1146162464.182.png

1146162464.183.png

1146162464.184.png

1146162464.185.png

1146162464.186.png

1146162464.187.png

1146162464.189.png

1146162464.190.png

1146162464.191.png

1146162464.192.png

1146162464.193.png

1146162464.194.png

1146162464.195.png

1146162464.196.png

1146162464.197.png

Specifications GAL20V8

OUTPUT LOGIC MACROCELL (OLMC)

The following discussion pertains to configuring the output logic

macrocell. It should be noted that actual implementation is ac-

complished by development software/hardware and is completely

transparent to the user.

PAL Architectures

GAL20V8

Emulated by GAL20V8

Global OLMC Mode

20R8

Registered

There are three global OLMC configuration modes possible:

simple , complex , and registered . Details of each of these

modes is illustrated in the following pages. Two global bits, SYN

and AC0, control the mode configuration for all macrocells. The

XOR bit of each macrocell controls the polarity of the output in any

of the three modes, while the AC1 bit of each of the macrocells

controls the input/output configuration. These two global and 16

individual architecture bits define all possible configurations in a

GAL20V8 . The information given on these architecture bits is

only to give a better understanding of the device. Compiler soft-

ware will transparently set these architecture bits from the pin

definitions, so the user should not need to directly manipulate

these architecture bits.

20R6

Registered

20R4

Registered

20RP8

Registered

20RP6

Registered

20RP4

Registered

20L8

Complex

20H8

Complex

20P8

Complex

14L8

Simple

16L6

Simple

18L4

Simple

20L2

Simple

14H8

Simple

16H6

Simple

18H4

Simple

The following is a list of the PAL architectures that the GAL20V8

can emulate. It also shows the OLMC mode under which the

devices emulate the PAL architecture.

20H2

Simple

14P8

Simple

16P6

Simple

18P4

Simple

20P2

Simple

COMPILER SUPPORT FOR OLMC

Software compilers support the three different global OLMC

modes as different device types. These device types are listed

in the table below. Most compilers have the ability to automati-

cally select the device type, generally based on the register usage

and output enable (OE) usage. Register usage on the device

forces the software to choose the registered mode. All combina-

torial outputs with OE controlled by the product term will force the

software to choose the complex mode. The software will choose

the simple mode only when all outputs are dedicated combinatorial

without OE control. The different device types listed in the table

can be used to override the automatic device selection by the

software. For further details, refer to the compiler software

manuals.

In registered mode pin 1 and pin 13 (DIP pinout) are permanently

configured as clock and output enable, respectively. These pins

cannot be configured as dedicated inputs in the registered mode.

In complex mode pin 1 and pin 13 become dedicated inputs and

use the feedback paths of pin 22 and pin 15 respectively. Because

of this feedback path usage, pin 22 and pin 15 do not have the

feedback option in this mode.

In simple mode all feedback paths of the output pins are routed

via the adjacent pins. In doing so, the two inner most pins ( pins

18 and 19) will not have the feedback option as these pins are

always configured as dedicated combinatorial output.

When using compiler software to configure the device, the user

must pay special attention to the following restrictions in each

mode.

Registered

Complex

Simple

Auto Mode Select

ABEL

P20V8R

P20V8C

P20V8AS

P20V8

CUPL

G20V8MS

G20V8MA

G20V8AS

G20V8

LOG/iC

GAL20V8_R

GAL20V8_C7

GAL20V8_C8

GAL20V8

OrCAD-PLD

"Registered" 1

"Complex" 1

"Simple" 1

GAL20V8A

PLDesigner

P20V8R 2

P20V8C 2

P20V8C 2

P20V8A

TANGO-PLD

G20V8R

G20V8C

G20V8AS 3

G20V8

1) Used with Configuration keyword.

2) Prior to Version 2.0 support.

3) Supported on Version 1.20 or later.

3

1146162464.198.png

1146162464.199.png

1146162464.200.png

1146162464.201.png

1146162464.202.png

1146162464.204.png

1146162464.205.png

1146162464.206.png

1146162464.207.png

1146162464.208.png

1146162464.209.png

1146162464.210.png

1146162464.211.png

1146162464.212.png

1146162464.213.png

1146162464.215.png

1146162464.216.png

1146162464.217.png

1146162464.218.png

1146162464.219.png

1146162464.220.png

1146162464.221.png

1146162464.222.png

1146162464.223.png

1146162464.224.png

1146162464.226.png

1146162464.227.png

1146162464.228.png

1146162464.229.png

1146162464.230.png

1146162464.231.png

1146162464.232.png

1146162464.233.png

1146162464.234.png

1146162464.235.png

1146162464.236.png

1146162464.237.png

1146162464.239.png

1146162464.240.png

1146162464.241.png

Specifications GAL20V8

REGISTERED MODE

In the Registered mode, macrocells are configured as dedicated

registered outputs or as I/O functions.

mode. Dedicated input or output functions can be implemented

as subsets of the I/O function.

Architecture configurations available in this mode are similar to

the common 20R8 and 20RP4 devices with various permutations

of polarity, I/O and register placement.

Registered outputs have eight product terms per output. I/Os have

seven product terms per output.

The JEDEC fuse numbers, including the User Electronic Signature

(UES) fuses and the Product Term Disable (PTD) fuses, are

shown on the logic diagram on the following page.

All registered macrocells share common clock and output enable

control pins. Any macrocell can be configured as registered or

I/O. Up to eight registers or up to eight I/Os are possible in this

CLK

Registered Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=0 defines this output configuration.

- Pin 1 controls common CLK for the registered outputs.

- Pin 13 controls common OE for the registered outputs.

- Pin 1 & Pin 13 are permanently configured as CLK &

OE.

DQ

Q

XOR

OE

Combinatorial Configuration for Registered Mode

- SYN=0.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1 defines this output configuration.

- Pin 1 & Pin 13 are permanently configured as CLK &

OE.

XOR

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

4

1146162464.242.png

1146162464.243.png

1146162464.244.png

1146162464.245.png

1146162464.246.png

1146162464.247.png

1146162464.248.png

1146162464.249.png

1146162464.250.png

1146162464.252.png

1146162464.253.png

1146162464.254.png

1146162464.255.png

1146162464.256.png

1146162464.257.png

1146162464.258.png

1146162464.259.png

1146162464.260.png

1146162464.261.png

1146162464.263.png

1146162464.264.png

1146162464.265.png

1146162464.266.png

1146162464.267.png

1146162464.268.png

1146162464.269.png

1146162464.270.png

1146162464.271.png

1146162464.272.png

1146162464.274.png

1146162464.275.png

1146162464.276.png

1146162464.277.png

1146162464.278.png

1146162464.279.png

1146162464.280.png

1146162464.281.png

1146162464.282.png

1146162464.283.png

1146162464.284.png

1146162464.285.png

1146162464.286.png

1146162464.287.png

1146162464.288.png

1146162464.289.png

Specifications GAL20V8

REGISTERED MODE LOGIC DIAGRAM

DIP (PLCC) Package Pinouts

1(2)

2640

0

4

8

12

16

20

24

28

32

36

PTD

2(3)

23(27)

0000

OLMC

22(26)

XOR-2560

AC1-2632

0280

3(4)

0320

OLMC

21(25)

XOR-2561

AC1-2633

0600

4(5)

0640

OLMC

20(24)

XOR-2562

AC1-2634

0920

5(6)

0960

OLMC

19(23)

XOR-2563

AC1-2635

1240

6(7)

1280

OLMC

18(21)

XOR-2564

AC1-2636

1560

7(9)

1600

OLMC

17(20)

XOR-2565

AC1-2637

1880

8(10)

1920

OLMC

16(19)

XOR-2566

AC1-2638

2200

9(11)

2240

OLMC

15(18)

XOR-2567

AC1-2639

2520

10(12)

11(13)

14(17)

OE

13(16)

2703

SYN-2704

AC0-2705

5

1146162464.291.png

1146162464.292.png

1146162464.293.png

1146162464.294.png

1146162464.295.png

1146162464.296.png

1146162464.297.png

1146162464.298.png

1146162464.299.png

1146162464.300.png

1146162464.302.png

1146162464.303.png

1146162464.304.png

1146162464.305.png

1146162464.306.png

1146162464.307.png

1146162464.308.png

1146162464.309.png

1146162464.310.png

1146162464.311.png

1146162464.313.png

1146162464.314.png

1146162464.315.png

1146162464.316.png

1146162464.317.png

1146162464.318.png

1146162464.319.png

1146162464.320.png

1146162464.321.png

1146162464.322.png

1146162464.324.png

1146162464.325.png

1146162464.326.png

1146162464.327.png

1146162464.328.png

1146162464.329.png

1146162464.330.png

1146162464.331.png

1146162464.332.png

1146162464.333.png

1146162464.334.png

1146162464.335.png

1146162464.336.png

1146162464.337.png

1146162464.338.png

1146162464.339.png

1146162464.340.png

1146162464.342.png

1146162464.343.png

1146162464.344.png

1146162464.345.png

1146162464.346.png

1146162464.347.png

1146162464.348.png

1146162464.349.png

1146162464.350.png

1146162464.351.png

1146162464.352.png

1146162464.353.png

1146162464.354.png

1146162464.355.png

1146162464.356.png

1146162464.357.png

1146162464.358.png

1146162464.359.png

1146162464.360.png

1146162464.361.png

1146162464.363.png

1146162464.364.png

1146162464.365.png

1146162464.366.png

1146162464.367.png

1146162464.368.png

1146162464.369.png

1146162464.370.png

1146162464.371.png

1146162464.372.png

1146162464.374.png

1146162464.375.png

1146162464.376.png

1146162464.377.png

1146162464.378.png

1146162464.379.png

1146162464.380.png

1146162464.381.png

1146162464.382.png

1146162464.383.png

1146162464.385.png

Plik z chomika:

Inne pliki z tego folderu:

1N4148.PDF (46 KB)
AT43312.PDF (157 KB)
BC547.PDF (70 KB)
BC557.PDF (70 KB)
BAT43.PDF (96 KB)

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin