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MT8888C/MT8888C-1
Integrated DTMF Transceiver
with Intel Micro Interface
Features
ISSUE 3
September 1995
• Central office quality DTMF transmitter/receiver
• Low power consumption
• High speed Intel micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
Ordering Information
MT8888CE/CE-1 20 Pin Plastic DIP
MT8888CC/CC-1 20 Pin Ceramic DIP
MT8888CS/CS-1 20 Pin SOIC
MT8888CN/CN-1 24 Pin SSOP
-40
°
C to +85
°
C
Applications
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
The MT8888C-1 is functionally identical to the
MT8888C except the receiver is enhanced to accept
lower level signals, and also has a specified low
signal rejection level.
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
TONE
å
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Data
Bus
Buffer
D0
D1
D2
D3
Status
Register
Tone Burst
Gating Cct.
Control
Logic
Interrupt
Logic
IRQ/CP
IN+
+
-
Dial
Tone
Filter
Control
Register
A
IN-
High Group
Filter
Digital
Algorithm
and Code
Converter
RD
GS
Control
Register
B
I/O
Control
CS
Low Group
Filter
OSC1
Oscillator
Circuit
R/W
OSC2
RS0
Control
Logic
Receive Data
Register
Bias
Circuit
Steering
Logic
V
DD
V
Ref
V
SS
ESt
St/GT
Figure 1 - Functional Block Diagram
4-91
MT8888C/MT8888C-1
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TO
NE
R
/W
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ
/CP
RD
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ
/CP
RD
RS0
NC
12
NC
TO
NE
R
/W
CS
16
11
15
14
13
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20 24
Name
Description
1
1
IN+
Non-inverting
op-amp input.
2
2
IN-
Inverting
op-amp input.
33 S
Gain Select
. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44
Ref
Reference Voltage
output (V
DD
/2).
55
SS
Ground (0V).
6
6 OSC1
Oscillator
input. This pin can also be driven directly by an external clock.
7
7 OSC2
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8
10 TONE Output from internal DTMF transmitter.
91 WR
Write
microprocessor input. TTL compatible.
10 12
CS
Chip Select
input. Active Low. This signal must be qualified externally by address latch
enable (ALE) signal, see Figure 12.
11 13
RS0
Register Select
input. Refer to Table 3 for bit interpretation. TTL compatible.
12 14
RD
Read
microprocessor input. TTL compatible.
13 15
IRQ/
CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14-
17
18-
21
D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.
TTL compatible.
18 22
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23 St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24
V
DD
Positive power supply (5V typ.).
8,9
16,17
NC No Connection.
4-92
MT8888C/MT8888C-1
Functional Description
The MT8888C/MT8888C-1 Integrated DTMF
Transceiver consists of a high performance DTMF
receiver with an internal gain setting amplifier and a
DTMF generator which employs a burst counter to
synthesize precise tone bursts and pauses. A call
progress mode can be selected so that frequencies
within the specified passband can be detected. The
Intel micro interface allows microcontrollers, such as
the 8080, 80C31/51 and 8085, to access the
MT8888C/MT8888C-1 internal registers.
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
Input Configuration
V
Ref
MT8888C/
MT8888C-
1
The input arrangement of the MT8888C/MT8888C-1
provides a differential-input operational amplifier as
well as a bias source (V
Ref
), which is used to bias the
inputs at V
DD
/2. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
gain adjustment. In a single-ended configuration, the
input pins are connected as shown in Figure 3.
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
W
R2 = 60k
W
, R3 = 37.5 k
W
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) - R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/
w
C)
2
Figure 4 shows the necessary connections for a
differential input configuration.
Receiver Section
Figure 4 - Differential Input Configuration
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Table 1). These
filters incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at the
frequencies of the incoming DTMF signals.
F
LOW
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
1209
1
0
0
0
1
697
1336
2
0
0
1
0
697
1477
3
0
0
1
1
770
1209
4
0
1
0
0
770
1336
5
0
1
0
1
770
1477
6
0
1
1
0
852
1209
7
0
1
1
1
852
1336
8
1
0
0
0
IN+
852
1477
9
1
0
0
1
941
1336
0
1
0
1
0
C
R
IN
IN-
941
1209
*
1
0
1
1
941
1477
#
1
1
0
0
R
F
GS
697
1633
A
1
1
0
1
770
1633
B
1
1
1
0
V
Ref
MT8888C/
MT888
8
C-1
852
1633
C
1
1
1
1
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
941
1633
D
0
0
0
0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1. Functional Encode/Decode Table
Figure 3 - Single-Ended Input Configuration
4-93
MT8888C/MT8888C-1
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
V
DD
MT8888C-
1
V
DD
C1
St/GT
Vc
ESt
R1
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
Steering Circuit
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the following inequalities
(see Figure 7):
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status re
giste
r. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
t
REC
³
t
DPmax
+t
GTPmax
- t
DAmin
t
REC
£
t
DPmin
+t
GTPmin
- t
DAmax
t
DAmax
+t
GTAmax
- t
DPmin
t
DO
£
t
DAmin
+t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1
m
F is recommended for most
t
GTP
= (R
P
C1) In [V
DD
/ (V
DD
-V
TSt
)]
t
GTA
= (R1C1) In (V
DD
/V
TSt
)
V
DD
R
P
= (R1R2) / (R1 + R2)
C1
St/GT
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
R1
R2
ESt
a) decreasing tGTP; (tGTP < tGTA)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
V
DD
t
GTA
= (R
p
C1) In (V
DD
/V
TSt
)
R
P
= (R1R2) / (R1 + R2)
C1
St/GT
R1
R2
ESt
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
4-94
MT8888C/
t
ID
³
MT8888C/MT8888C-1
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independent tone present (t
GTP
) and
tone absent (t
GTA
) guard times. This may be
necessary to meet system specifications which place
both accept and reject limits on tone duration and
interdigital pause. Guard time adjustment also allows
the designer to tailor system parameters such as talk
off and noise immunity.
mode has been selected. DTMF signals cannot be
detected if CP mode has been selected (see Table
7). Figure 8 indicates the useful detect bandwidth of
the call progress filter. Frequencies presented to the
input, which are within the ‘accept’ bandwidth limits
of the filter, are ha
rd-li
mited by a high gain
comparator with the IRQ/CP pin serving as the
output. The squarewave output obtained from the
schmitt trigger can be analyzed by a microprocessor
or counter arrangement to determine the nature of
the call progress tone being detected. Frequencies
which are in the ‘r
ejec
t’ area will not be detected and
consequently the IRQ/CP pin will remain low.
Increasing t
REC
improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t
REC
with a long t
DO
would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
LEVEL
(dBm)
-25
Call Progress Filter
0
250
500
750
A call progress mode, using the MT8888C/
MT8888C-1, can be selected allowing the detection
of various tones, which identify the progress of a
telephone call on the network. The call progress
tone input and DTMF input are common, however,
call progress tones can only be detected when CP
= Reject
FREQUENCY (Hz)
= May Accept
= Accept
Figure 8 - Call Progress Response
EVENTS
A
B
C
D
E
F
t
RE
C
t
REC
t
ID
t
DO
V
in
TONE #n
TONE
#n + 1
TONE
#n + 1
t
DP
t
DA
ESt
t
GTP
t
GTA
St/GT
V
TSt
t
PStRX
RX
0
-RX
3
DECODED TONE # (n-1)
# n
# (n + 1)
t
PStb3
b3
b2
Read
Status
Register
IRQ/CP
Figure 7 - Receiver Timing Diagram
4-95
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