DS1267.PDF

DS1267

Dual Digital Potentiometer Chip

FEATURES

•

PIN ASSIGNMENT

Ultra low power consumption, quiet, pumpless design

V CC

•

Two digitally controlled, 256–position potentiometers

S OUT

RST

CLK

GND

V CC

•

Serial port provides means for setting and reading

both potentiometers

S OUT

•

Resistors can be connected in series to provide

increased total resistance

RST

CLK

C OUT

•

14–pin DIP, 16–pin SOIC, 20–pin TSSOP packages

C OUT

GND

•

Resistive elements are temperature compensated to

± 0.3 LSB relative linearity

14–PIN DIP (300 MIL)

16–PIN SOIC (300 MIL)

See Mech. Drawings

Section

•

Standard resistance values:

– DS1267–10 10K W

– DS1267–50

V CC

– DS1267–100 100K W

50K

S OUT

•

Operating Temperature Range

– –40 ° C to +85 ° C

RST

CLK

GND

C OUT

DESCRIPTION

The DS1267 consists of two digitally controlled solid–

state potentiometers. Each potentiometer is composed

of 256 resistive sections. Between each resistive sec-

tion and both ends of the potentiometer are tap points

which are accessible to the wiper. The position of the

wiper on the resistive array is set by an 8–bit value that

controls which tap point is connected to the wiper output.

Communication and control of the device are accom-

plished via a 3–wire serial port interface. This interface

allows the device wiper position to be read or written.

20–PIN TSSOP (173 MIL)

PIN DESCRIPTION

L0, L1

– Low End of Resistor

H0, H1

– High End of Resistor

W0, W1

– Wiper Terminal of Resistor

V B

– Substrate Bias Voltage

S OUT

– Stacked Configuration Output

RST

– Serial Port Reset Input

– Serial Port Data Input

Both potentiometers can be connected in series (or

stacked) for an increased total resistance with the same

resolution. For multiple device single processor environ-

ments, the DS1267 can be cascaded or daisy chained.

This feature provides for control of multiple devices over

a single 3–wire bus.

CLK

– Serial Port Clock Input

C OUT

– Cascade Port Output

V CC

– +5 Volt Supply

GND

– Ground

– No Internal Connection

020599 1/10

DS1267

The DS1267 is offered in three standard resistance val-

ues which include 10K, 50K, and 100K ohm versions.

Available packages for the device include a 14–pin DIP,

16–pin SOIC, and 20–pin TSSOP.

Figure 9(a) presents the 3–wire serial port p rotoc ol. As

shown, the 3–wire port is inactive when the RST signal

input is low. Commu nica tion with the DS1267 requires

the transistion of the RST input from a low state to a high

state. Once the 3–wire port has been activated, data is

entered into the part on the low to high transistion of the

CLK signal inputs. Three–wire serial timing require-

ments are provided in the timing diagrams of Figure

9(b),(c).

OPERATION

The DS1267 contains two 256–position potentiometers

whose wiper positions are set by an 8–bit value. These

two 8–bit values are written to a 17–bit I/O shift register

which is used to store the two wiper positions and the

stack select bit when the device is powered. A block dia-

gram of the DS1267 is presented in Figure 1.

Data written to the DS1267 over the 3–wire serial inter-

face is stored in the 17–bit I/O shift register (see

Figure 2). The 17–bit I/O shift register contains both

8–bit potentiometer wiper position values and the stack

select bit. The composition of the I/O shift register is

presented in Figure 2. Bit 0 of the I/O shift register con-

tains the stack select bit. This bit will be discussed in the

section entitled Stacked Configuration. Bits 1 through 8

of the I/O shift register contain the potentiometer–1 wiper

position value. Bit 1 will contain the MSB of the wiper set-

ting for potentiometer–1 and bit 8 the LSB for the wiper

setting. Bits 9 through 16 of the I/O shift register contain

the value of the potentiometer–0 wiper position with the

MSB for the wiper position occupying bit 9 and the LSB bit

16.

Communication and control of the DS1267 is accom-

plished through a 3–wire serial port interface that drives

an internal control logic unit. The 3– wire serial interface

consists of the three input signals: RST, CLK, and DQ.

The RST control signal is used to enable the 3–wire serial

port o peration of the d evice. The Chip is selected when

RST is high and RST must be high to begin any commu-

nication to the DS1267. The CLK signal input is used to

provide timing synchronization for data input and output.

The DQ signal line is used to transmit potentiometer

wiper settings and the stack select bit configuration to the

17–bit I/O shift register of the DS1267.

DS1267 BLOCK DIAGRAM Figure 1

256–1 MULTIPLEXER

WIPER–0 8 BITS

WIPER–1 8 BITS

RST

STACK

MULTIPLEXER

S OUT

CLK

CONTROL

LOGIC

b16

17–BIT I/O SHIFT REGISTER

C OUT

020599 2/10

DS1267

I/O SHIFT REGISTER Figure 2

STACK SELECT BIT

b16

POTENTIOMETER–0

POTENTIOMETER–1

17–BIT I/O SHIFT REGISTER

Transmission of data always begins with the stack select

bit followed by the potentiometer–1 wiper position value

and lastly the potentiometer–0 wiper position value.

STACKED CONFIGURATION

The potentiometers of the DS1267 can be connected in

series as shown in Figure 3. This is referred to as the

stacked configuration. The stacked configuration allows

the user to double the total end–to–end resistance of the

part and the number of steps to 512 (or 9 bits of resolu-

tion).

When wiper position data is to be written to the DS1267,

17 bits (or some integer multiple) of data should always

be transmitted. Transactions which do not send a com-

plete 17–bits (or multiple) will leave the register incom-

plete and possibly an error in the desired wiper positions.

The wiper output for the combined stacked potentiome-

ter will be taken at the S OUT pin, which is the multiplexed

output of the wiper of potentiometer–0 (W0) or potentiom-

eter–1 (W1). The potentiometer wiper selected at the

S OUT output is governed by the setting of the stack select

bit (bit 0) of the 17–bit I/O shift register. If the stack select

bit has value 0, the multiplexed output, S OUT , will be that

of the potentiometer–0 wiper. If the stack select bit has

value 1, the multiplexed output, S OUT , will be that of the

potentiometer–1wiper.

Afte r a c ommunication transaction has been completed

the RST signal input should be taken to a low state to pre-

vent a ny ina dvertent changes to the device shift register.

Once RST has reached a low state, the contents of the

I/O shift register are loaded into the respective multiplex-

ers for setting wiper pos ition. A new wiper position will

only engage after a RST transition to the inactive state.

On device power–up the DS1267 wiper positions will be

set at 50% of the total resistance or binary value 1000

0000.

STACKED CONFIGURATION Figure 3

POTENTIOMETER–1

STACK

MULTIPLEXER

S OUT

POTENTIOMETER–0

020599 3/10

DS1267

CASCADE OPERATION

A feature of the DS1267 is the ability to control multiple

devices from a single processor. Multiple DS1267s can

be linked or daisy chained as shown in Figure 4. As a

data bit is entered into the I/O shift register of the DS1267

a bit will appear at the C OUT output within a maximum

delay of 50 nanoseconds. The stack select bit of the

DS1267 will always be the first out the part at the begin-

ning of a transaction. Additionall y the C OUT pin is always

active regardless of the state of RST. This allows one to

read the I/O shift register without changing its value.

CASCADING MULTIPLE DEVICES Figure 4

PROCESSOR

C OUT

DS1267

C OUT

OPTIONAL FEEDBACK RESISTOR

FOR READING DATA (2K TO 10K)

The C OUT output of the DS1267 can be used to drive the

DQ input of another DS1267. When connecting multiple

devices, the total number of bits transmitted is always 17

times the number of DS1267s in the daisy chain.

ABSOLUTE AND RELATIVE LINEARITY

Absolute linearity is defined as the difference between

the actual measured output voltage and the expected

output voltage. Figure 5 presents the test circuit used to

measure absolute linearity. Absolute linearity is given in

terms of a minimum increment or expected output when

the wiper is moved one position. In the case of the test

circuit, a minimum increment (MI) or one LSB would

equal 10/512 volts. The equation for absolute linearity is

given as follows:

An optional feedback resistor can be placed between the

C OUT terminal of the last device and the first DS1267 DQ

input thus allowing the controlling processor to read, as

well as, write data, or circularly clock data through the

daisy chain. The value of the feedback or isolation resis-

tor should be in the range from 1K to 10K ohms.

(1)

ABSOLUTE LINEARITY

AL={V O (actual) – V O (expected)}/MI

When reading data via the C OUT pin and isolation resis-

tor, th e DQ line is left floating by the reading device.

When RST is driven high, bit 17 is present on the C OUT

pin, which is fed back to the input DQ pin through the

isolation resistor. When the CLK input transitions low to

high, bit 17 is loaded into the first position of the I/O shift

the next device. After 17 bits (or 17 times the number of

DS1267s in the daisy chain), the data has shifted com-

plete ly around and back to its original position. When

RST transitions to the low state to end data transfer, the

value (the same as before the read occurred) is loaded

into the wiper–0, wiper–1, and stack select bit I/O regis-

ter.

Relative Linearity is a measure of error between two

adjacent wiper position points and is given in terms of MI

by equation (2).

(2)

RELATIVE LINEARITY

RL={V O (n+1) – V O (n)}/MI

C. The spec-

ification for absolute linearity of the DS1267 is ± 0.75 MI

typical. The specification for relative linearity of the

DS1267 is ± 0.3 MI typical.

020599 4/10

Figure 6 is a plot of absolute linearity and relative linearity

versus wiper position for the DS1267 at 25

DS1267

LINEARITY MEASUREMENT CONFIGURATION Figure 5

+5V

POTENTIOMETER–1

RW1

STACK

MULTIPLEXER

S OUT

I 0 =0

V O

RW0

POTENTIOMETER–0

–

–5V

NOTE:

In this setup, a

2% delta in total resistance R0 to R1 would cause a

2.5 MI error.

DS1267 ABSOLUTE AND RELATIVE LINEARITY Figure 6

Absolute and Relative Linearity

(Normalized To 1 LSB)

0.8

0.6

0.4

0.2

R e lati v e

LSB

–0.2

–0.4

Absolute

–0.6

–0.8

–1

100

150

200

250

300

350

400

450

500

Wiper Setting

020599 5/10

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