MAT02.PDF

Low Noise, Matched

Dual Monolithic Transistor

MAT02

FEATURES

Low Offset Voltage: 50 m V max

Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/ Ö Hz max

High Gain (h FE ): 500 min at I C = 1 mA

300 min at I C = 1 m A

Excellent Log Conformance: r BE . 0.3 V

Low Offset Voltage Drift: 0.1 m V/ 8 C max

Improved Direct Replacement for LM194/394

Available in Die Form

PIN CONNECTION

TO-78

(H Suffix)

NOTE

Substrate is connected to case on TO-78 package. Sub-

strate is normally connected to the most negative circuit

potential, but can be floated.

PRODUCT DESCRIPTION

The design of the MAT02 series of NPN dual monolithic tran-

sistors is optimized for very low noise, low drift, and low r BE .

Precision Monolithics’ exclusive Silicon Nitride “Triple-

Passivation” process stabilizes the critical device parameters

over wide ranges of temperature and elapsed time. Also, the high

current gain (h FE ) of the MAT02 is maintained over a wide

range of collector current. Exceptional characteristics of the

MAT02 include offset voltage of 50 mV max (A/E grades) and

150 mV max F grade. Device performance is specified over the

full military temperature range as well as at 25°C.

Input protection diodes are provided across the emitter-base

junctions to prevent degradation of the device characteristics

due to reverse-biased emitter current. The substrate is clamped

to the most negative emitter by the parasitic isolation junction

created by the protection diodes. This results in complete isola-

tion between the transistors.

The MAT02 should be used in any application where low noise

is a priority. The MAT02 can be used as an input sta g e to make

an amplifier with noise voltage of less than 1.0 nV/ÖHz at 100 Hz.

Other applications, such as log/antilog circuits, may use the ex-

cellent logging conformity of the MAT02. Typical bulk resis-

tance is only 0.3 W to 0.4 W. The MAT02 electrical charac-

teristics approach those of an ideal transistor when operated over

a collector current range of 1 mA to 10 mA. For applications re-

quiring multiple devices see MAT04 Quad Matched Transistor

data sheet.

ABSOLUTE MAXIMUM RATINGS 1

Collector-Base Voltage (BV CBO ) . . . . . . . . . . . . . . . . . . . . 40 V

Collector-Emitter Voltage (BV CEO ) . . . . . . . . . . . . . . . . . . 40 V

Collector-Collector Voltage (BV CC ) . . . . . . . . . . . . . . . . . . 40 V

Emitter-Emitter Voltage (BV EE ) . . . . . . . . . . . . . . . . . . . . . 40 V

Collector Current (I C ) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Emitter Current (I E ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Total Power Dissipation

Case Temperature

C 2

. . . . . . . . . . . . . . . . . . . . . 1.8 W

Ambient Temperature

C 3

. . . . . . . . . . . . . . . . 500 mW

Operating Temperature Range

MAT02A . . . . . . . . . . . . . . . . . . . . . . . . . . –55

C to +125

MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . –25

C to +85

Operating Junction Temperature . . . . . . . . . . –55

C to +150

Storage Temperature . . . . . . . . . . . . . . . . . . . –65

C to +150

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300

Junction Temperature . . . . . . . . . . . . . . . . . . –65

C to +150

NOTES

1 Absolute maximum ratings apply to both DICE and packaged devices.

2 Rating applies to applications using heat sinking to control case temperature.

Derate linearly at 16.4 mW/°C for case temperature above 40°C.

3 Rating applies to applications not using a heat sinking; devices in free air only.

Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.

ORDERING GUIDE 1

V OS max

Temperature

Package

Model

(T A = +25 8 C) Range

Option

MAT02AH 2

–55

C to +125

C TO-78

MAT02EH

–55

C to +125

C TO-78

MAT02FH

150

–55

C to +125

C TO-78

NOTES

1 Burn-in is available on commercial and industrial temperature range parts in

TO-can packages.

2 For devices processed in total compliance to MIL-STD-883, add /883 after part

number. Consult factory for 883 data sheet.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

MAT02–SPECIFICATIONS (@ V CB = 15 V, I C = 10 m A, T A = 25 8 C, unless otherwise noted.)

MAT02A/E

MAT02F

Parameter

Symbol

Conditions

Min Typ Max Min Typ

Max

Units

Current Gain

h FE

I C = 1 mA 1

500 605

400 605

I C = 100

500 590

400 590

I C = 10

400 550

300 550

I C = 1

300 485

200 485

Current Gain Match

h FE

I C

1 mA 2

0.5

Offset Voltage

V OS

V CB = 0, 1

I C

1 mA 3

150

Offset Voltage

V OS /

V CB 0

V CB

V MAX , 4

Change vs. V CB

I C

1 mA 3

Offset Voltage Change

V OS /

I C

V CB = 0 V

vs. Collector Current

I C

1 mA 3

Offset Current

Change vs. V CB

I OS /

V CB 0

V CB

V MAX

pA/V

Bulk Resistance

r BE

I C

10 mA 5

0.3

0.5

0.3

0.5

Collector-Base

Leakage Current

I CBO

V CB = V MAX

200

400

Collector-Collector

Leakage Current

I CC

V CC = V MAX 5, 6

200

400

Collector-Emitter

V CE = V MAX 5, 6

Leakage Current

I CES

V BE = 0

200

400

Noise Voltage Density

e n

I C = 1 mA, V CB = 0 7

f O = 10 Hz

1.6

nV/

f O = 100 Hz

0.9

nV/

f O = 1 kHz

0.85 1

0.85 2

nV/

f O = 10 kHz

0.85 1

0.85 2

nV/

Collector Saturation

Voltage

V CE(SAT)

I C = 1 mA, I B = 100

0.05 0.1

0.05 0.2

Input Bias Current

I B

I C = 10

Input Offset Current

I OS

I C = 10

0.6

1.3

Breakdown Voltage

BV CEO

Gain-Bandwidth Product f T

I C = 10 mA, V CE = 10 V

200

MHz

Output Capacitance

C OB

V CB = 15 V, I E = 0

Collector-Collector

Capacitance

C CC

V CC = 0

NOTES

1 Current gain is guaranteed with Collector-Base Voltage (V CB ) swept from 0 to V MAX at the indicated collector currents.

2 Current gain match (Dh FE ) is defined as: Dh FE =

3 Measured at I C = 10 mA and guaranteed by design over the specified range of I C .

4 This is the maximum change in V OS as V CB is swept from 0 V to 40 V.

5 Guaranteed by design.

6 I CC and I CES are verified by measurement of I CBO .

7 Sample tested.

Specifications subject to change without notice.

100 (

I B ) (h FE min)

I C

–2–

REV. C

ELECTRICAL CHARACTERISTICS

MAT02

ELECTRICAL CHARACTERISTICS

(V CB = 15 V, –25

T A £

+85

C, unless otherwise noted.)

MAT02E

MAT02F

Parameter

Symbol

Conditions

Min Typ Max

Units

Offset Voltage

V OS

V CB = 0

220

1 mA £ I C £ 1 mA 1

Average Offset

Voltage Drift

TCV OS

10 mA £ I C £ 1 mA, 0 £ V CB £ V MAX 2

0.08 0.3

0.08 1

mV/°C

V OS Trimmed to Zero 3

0.03 0.1

0.03 0.3

Input Offset Current I OS

I C = 10 mA

Input Offset

Current Drift

TCI OS

I C = 10 mA 4

40 90

40 150

pA/°C

Input Bias Current

I B

I C = 10 mA

Current Gain

h FE

I C = 1 mA 5

325

300

I C = 100 mA

275

250

I C = 10 mA

225

200

I C = 1 mA

200

150

Collector-Base

I CBO

V CB = V MAX

Leakage Current

Collector-Emitter

I CES

V CE = V MAX , V BE = 0

Leakage Current

Collector-Collector

I CC

V CC = V MAX

Leakage Current

ELECTRICAL CHARACTERISTICS (V CB = 15 V, –55 8 C £ T A £ +125 8 C, unless otherwise noted.)

MAT02A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Offset Voltage

V OS

V CB = 0

1 mA £ I C £ 1 mA 1

Average Offset

Voltage Drift

TCV OS

10 mA £ I C £ 1 mA, 0 £ V CB £ V MAX 2

0.08

0.3

mV/°C

V OS Trimmed to Zero 3

0.03

0.1

mV/°C

Input Offset Current

I OS

I C = 10 mA

Input Offset

Current Drift

TCI OS

I C = 10 mA 4

pA/°C

Input Bias Current

I B

I C = 10 mA

Current Gain

h FE

I C = 1 mA 5

275

I C = 100 mA

225

I C = 10 mA

125

I C = 1 mA

150

Collector-Base

I CBO

V CB = V MAX

Leakage Current

T A = 125°C

Collector-Emitter

I CES

V CE = V MAX , V BE = 0

Leakage Current

T A = 125°C

Collector-Collector

I CC

V CC = V MAX

Leakage Current

T A = 125°C

NOTES

1 Measured at I C = 10 mA and guaranteed by design over the specified range of I C .

V OS

T for V OS ! V BE ) T = 298 ° K for T A = 25°C.

3 The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at T A = 25

C. This ratio must be held to 0.003% over

the entire temperature range. Measurements are taken at the temperature extremes and 25

4 Guaranteed by design.

5 Current gain is guaranteed with Collector-Base Voltage (V CB ) swept from 0 to V MAX at the indicated collector current.

Specifications subject to change without notice.

REV. C

–3–

2 Guaranteed by V OS test (TCV OS @

MAT02

WAFER TEST LIMITS

(@ 25

C for V CB = 15 V and I C = 10

A, unless otherwise noted.)

MAT02N

Parameter

Symbol

Conditions

Limits

Units

Breakdown Voltage

BV CEO

V min

Offset Voltage

V OS

10 mA £ I C £ 1 mA 1

150

mV max

Input Offset Current

I OS

1.2

nA max

Input Bias Current

I B

V CB = 0 V

nA max

Current Gain

h FE

I C = 1 mA, V CB = 0 V

400

min

I C = 10 mA, V CB = 0 V

300

Current Gain Match

Dh FE

10 mA £ I C £ 1 mA, V CB = 0 V

% max

Offset Voltage

DV OS /DV CB

0 V £ V CB £ 40 V

mV max

Change vs. V CB

10 mA £ I C £ 1 mA 1

Offset Voltage Change

DV OS /DI C

V CB = 0

mV max

vs. Collector Current

10 mA £ I C £ 1 mA 1

Bulk Resistance

r BE

100 mA £ I C £ 10 mA

0.5

W max

Collector Saturation Voltage

V CE (SAT)

I C = 1 mA

0.2

V max

I B = 100 mA

A and guaranteed by design over the specified range of I C .

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

TYPICAL ELECTRICAL CHARACTERISTICS

(V CB = 15 V, I C = 10

A, T A = +25

C, unless otherwise noted.)

MAT02N

Parameter

Symbol

Conditions

Limits

Units

Average Offset

TCV OS

10 mA £ I C £ 1 mA

0.08

mV/°C

Voltage Drift

0 £ V CB £ V MAX

Average Offset

TCI OS

I C = 10 mA

pA/°C

Current Drift

Gain-Bandwidth

f T

V CE = 10 V, I C = 10 mA

200

MHz

Product

Offset Current Change vs. V CB

DI OS /DV CB

0 £ V CB £ 40 V

pA/V

DICE CHARACTERISTICS

1. COLLECTOR (1)

2. BASE (1)

3. EMITTER (1)

4. COLLECTOR (2)

5. BASE (2)

6. EMITTER (2)

7. SUBSTRATE

Die Size 0.061 ´ 0.057 inch, 3,477 sq. mils

(1.549 ´ 1.448 mm, 224 sq. mm)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the MAT02 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. C

NOTES

1 Measured at l C = 10

MAT02

Figure 1. Current Gain vs.

Collector Current

Figure 2. Current Gain

vs. Temperature

Figure 3. Gain Bandwidth

vs. Collector Current

Figure 4. Base-Emitter-On

Voltage vs. Collector Current

Figure 5. Small Signal Input

Resistance vs. Collector Current

Figure 6. Small-Signal Output

Conductance vs. Collector Current

Figure 7. Saturation Voltage

vs. Collector Current

Figure 8. Noise Voltage

Density vs. Frequency

Figure 9. Noise Voltage Density

vs. Collector Current

REV. C

–5–

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